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Intel 815 manual 1. ST00Input Status, Bit

Models: 815

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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

9.1.1.ST00Input Status 0

I/O (and Memory Offset) Address:							3C2h
Default:							00h
Attributes:							Read Only
7			6			5	4	3		0
		CRT Int			Reserved (00)		RGB Cmp			Reserved (0000)
							/ Sen


		Bit						Descriptions

	7		CRT Interrupt Pending. Note that the generation of interrupts can be enabled, through bits [4,5] of the
			Vertical Retrace End Register (CR11). This ability to generate interrupts at the start of the vertical
			retrace interval is a feature that is typically unused by current software. This bit is here for EGA
			compatibility.
			0 = CRT (vertical retrace interval) interrupt is not pending.
			1 = CRT (vertical retrace interval) interrupt is pending

	6:5		Reserved. Read as 0s.

	4		RGB Comparator / Sense. This bit returns the state of the output of the RGB output comparator(s).
			BIOS uses this bit to determine whether the display is a color or monochrome CRT.
			0 = Monochrome
			1 = Color
			BIOS blanks the screen or clears the frame buffer to display only black. Next, BIOS configures the
			D-to-A converters and the comparators to test for the presence of a color display. Finally, if the BIOS
			does not detect any colors, it tests for the presence of a display. The result of each such test is read via
			this bit.

	3:0		Reserved. Read as 0s.

80

Image 80

Intel 815 manual 1. ST00Input Status, Bit

Contents

Intel 815 Chipset Graphics Controller Programmer’s Reference Manual PRMIntel 815 Chipset Graphics Controller PRM, Rev Contents 100 106 141 Monosrccopyimmediateblt Gfxrenderstatemaplodlimits 15.4.3.3 HORZPH-Horizontal Phase Register 279 15.4.3.4 16.2.5 Figures Tables Date Revision HistoryRev This page is intentionally left blank Term Description IntroductionTerminology Reference Documents MCHIntel 815 Chipset Overview I/O Controller Hub Intel 82815 Chipset Gmch OverviewIntel 82815 Chipset Gmch Block Diagram Host InterfaceMultiplexed AGP and Display Cache Interface Data Rate Signaling LevelSystem Memory Interface Hub Interface Intel 82815 Chipset Gmch Integrated Graphics SupportGmch Power Delivery Three PCI Devices on GmchSystem Clocking Front Side Bus System Memory Display Cache InterfaceSupported Single Monitor and Multi-monitor Configurations Multi-Mode Capability RequirementsConfiguration Single Monitor Multi-monitor Device Mode Auto-Detect Flowchart System StartupSoftware Start-Up Sequence Graphics Driver Startup Switching Device modes System Address Map System Memory SpaceMemory and I/O Space Registers Graphics Controller Register Memory and I/O MapReserved 50000h−5FFFFh. Reserved in the Intel 815 chipset Address Offset Symbol Register Name Access GC Register Memory Address MapVGA and VGA Extended Registers Instruction and Interrupt Control Registers 01000h −02FFFhInstpm OV0ADD Ssladd VGA and Extended VGA Register Map Display and Cursor Control Registers 70000h-7FFFFhVGA and Extended VGA I/O and Memory Register Map Address Register Name Read Register Name Write 2D RegistersIndex Sym Register Name Indirect VGA and Extended VGA Register IndicesIndex Sym Description 2D Attribute Controller Registers 3C0h / 3C1h CR0F Graphics Address Translation Memory Buffers for GC’s Instruction Interface GTTGraphics Translation Table GTT Range Definition This page is intentionally left blank Basic Initialization Procedures Vendor Id Device Id PCI Device CharacteristicsInitialization Sequence Hardware Detection ProbeFrame Buffer Initialization Hardware Register Initialization Hardware StateColor vs. Monochrome Monitors Protect Registers Locking and UnlockingSaving the Hardware State Restoring the Hardware State Intel 815 Chipset Graphics Controller PRM, Rev Intel 815 Chipset Graphics Controller PRM, Rev This page is intentionally left blank BLT Engine Programming Considerations When the Source and Destination Locations OverlapBlt Engine Programming Source Bblt3.vsd Destination Source Bblt4.vsd Basic Graphics Data Considerations Contiguous vs. Discontinuous Graphics DataSource Data Monochrome Source Data Pattern Data Pattern Data -- Always an 8x8 Array of PixelsBpp Pattern Data -- Occupies 64 Bytes 8 quadwords Destination Data BLT Programming Examples Pattern Fill -- a Very Simple BLTPattern Data for Example Pattern Fill BLT Results of Example Pattern Fill BLT Drawing Characters Using a Font Stored in System Memory On-Screen Destination for Example Character Drawing BLTIntel 815 Chipset Graphics Controller PRM, Rev Results of Example Character Drawing BLT Initialization Registers Standard VGA RegistersSmram Registers SMRAM-System Management RAM Control Register DeviceBit Description RAMInitialization and Usage of Stolen Memory Display and Cursor Control Registers Clock Control and Power Management RegistersLCD/TV-Out Graphics Controller Registers 3CEh / 3CFh CRT Controller Registers 3B4h/3D4h/3B5h/3D5hInitialization Values for VGA Registers MSRGR01 00h This page is intentionally left blank Frame Buffer Access Intel 815 Chipset Graphics Controller PRM, Rev VGA and Extended VGA Registers General Control & Status RegistersName Function Read Write Memory Offset1. ST00Input Status BitDisplay Enable Output ST01Input StatusBit Descriptions Vertical Retrace/VideoFCRFeature Control Reserved. Read as Vsync ControlCRT HSync Polarity MSRMiscellaneous OutputCRT VSync Polarity Sequencer Registers SRXSequencer Index2. SR00Sequencer Reset 3. SR01Clocking Mode Shift4. SR02Plane/Map Mask Bit 10,4 Map Number Table Location 5. SR03Character FontBit 32 Map Number Table Location 6. SR04Memory Mode Register Made according to the value of the Plane Mask Register SR027. SR07Horizontal Character Counter Reset Graphics Controller RegistersGRXGRX Graphics Controller Index Register Bit Description Horizontal Character Counter2. GR00Set/Reset Register 3. GR01Enable Set/Reset Register4. GR02Color Compare Register 5. GR03Data Rotate Register7. GR05Graphics Mode Register 6. GR04Read Plane Select RegisterBits 65=1x Bits 65=00Bits 65=01 Write Mode Odd/Even ModeRead Mode Bit Graphics/Text Mode8. GR06Miscellaneous Register Bit Mask 9. GR07Color Don’t Care Register10. GR08Bit Mask Register Reserved To Local Memory Enable Packed Mode Enable11. GR10Address Mapping VGA Buffer/Memory Map Select12. GR11Page Selector SupportedMemory Offset Address 3CFh Index=14h-1fh Default Attribute 13. GR141FSoftware FlagsAttribute Controller Registers ARXAttribute Controller Index Register2. AR000FPalette Registers 0F 3. AR10Mode Control RegisterPalette Bits P5, P4 Select Pixel Width/Clock SelectEnable Blinking/Select Background Intensity Enable Line Graphics Character CodeGraphics/Alphanumeric Mode Pixel Panning CompatibilityBit 54 ST01 Bit 5. AR12Memory Plane Enable Register4. AR11Overscan Color Register 6. AR13Horizontal Pixel Panning Register ReservedPixel Text Color Pixel Text GraphicsVGA Color Palette Registers 7. AR14Color Select RegisterDACMASKPixel Data Mask Register DACSTATEDAC State Register DACRXPalette Read Index RegisterDACWXPalette Write Index Register Bits Index Register IndicatedCRT Controller Register DACDATAPalette Data RegisterDisplay Fields and Dimensions CRxx Control Registers CRXCRT Controller Index Register4. CR02Horizontal Blanking Start Register 3. CR01Horizontal Display Enable End Register2. CR00Horizontal Total Register 6. CR04Horizontal Sync Start Register Bit Amount of Delay5. CR03Horizontal Blanking End Register 7. CR05Horizontal Sync End Register 8. CR06Vertical Total Register 9. CR07Overflow Register115 116 10. CR08Preset Row Scan Register Double Scanning Enable 11. CR09Maximum Scan Line Register12. CR0AText Cursor Start Register 13. CR0BText Cursor End Register14. CR0CStart Address High Register 15. CR0DStart Address Low Register 16. CR0EText Cursor Location High Register17. CR0FText Cursor Location Low Register 18. CR10Vertical Sync Start Register19. CR11Vertical Sync End Register 20. CR12Vertical Display Enable End Register CR13Offset RegisterCR146 CR176 Addressing Mode 22. CR14Underline Location RegisterCount By CR145 CR173 Address Incrementing Interval23. CR15Vertical Blanking Start Register 24. CR16Vertical Blanking End RegisterCR146 CR176 25. CR17CRT Mode ControlWord Mode or Byte Mode Compatibility Mode Support Select Row Scan CounterDWord Mode Memory Address Counter Address BitsFrame Buffer Address Decoder CR17 bit 1=1 CR17 bit 1=0 CR17 bit 0=1 CR17 bit 0=026. CR18Line Compare Register 27. CR22Memory Read Latch Data Register29. CR30Extended Vertical Total Register 30. CR31Extended Vertical Display End Register 31. CR32Extended Vertical Sync Start Register 32. CR33Extended Vertical Blanking Start Register Extended Horizontal Total MSB that extends CR00 33. CR35 Extended Horizontal Total Time Register34. CR39Extended Horizontal Blank Time Register 35. CR40Extended Start Address Register 36. CR41Extended Offset Register 37. CR42Extended Start Address High Register39. CR80I/O Control Interlace Enable38. CR70Interlace Control Register 40. CR81Reserved 41. CR82Blink Rate ControlOverview Programming InterfaceReserved Bits and Software Compatibility GC Register Programming GC Instruction StreamsInstruction Use Instruction Transport OverviewInstruction Parser Interrupt RingRing Buffers RB Ring Buffer RegistersRing Buffer Use Characteristic DescriptionRing Buffer Initialization Batch Buffers Batch Buffer SequenceWait Instructions Instruction ArbitrationArbitration Rationale Instruction Arbitration Rules Batch Buffer Protected ModeInstruction Arbitration Points Instructions Instruction FormatInstruction Parser Instructions Bits 3129 2824 210Graphics Controller Instructions Client InstructionClient Instruction Parser Instructions IntroductionInstruction Descriptions DWord Bit DescriptionReserved MBZ Opcode 01hOpcode 02h Gfxcmdparserwaitforevent DWord BitDWord Bits Description Dwordlength 00h Opcode 15hReserved 00000h Dword Length 00h Instruction Target 14hFlip type 0 Synch flip, 1 Async flip Opcode 16h Opcode 07hOpcode 08h Arbitration ON/OFFInstruction Target 11h Instruction Target 12hWord Bits Description Gfxcmdparserbatchbuffer Instruction Target 30hBLT Engine Instructions InstructionsBLTs To and From Cacheable Memory Setupblt Setup Background Color All Setup Foreground Color SLB & TB onlyInstruction Target Opcode 00h Dword Length 06hInstruction Target Opcode 10h Dword Length 07hColor Depth Raster OperationPixelblt Instruction Target Opcode 20hInstruction Target Opcode 21h Destination X2 Coordinate Ending RightDword Length 04h TextbltInstruction Target Opcode 22h TEXTImmediateBLT Instruction Target Opcode 30hImmediate Data DW Immediate Data DWs 2 through Dwordlength DWLColorblt Instruction Target Opcode 40hDword Length 03h Solid Pattern ColorPatblt Instruction Target Opcode 41hMono Pattern Transparency Mode 1 = transparency enabled MonopatbltInstruction Target Opcode 42h Pattern Background ColorSrccopyblt Instruction Target Opcode 43hInstruction Target Opcode 44h LineSource Background Color Source Foreground ColorMono Source Transparency Mode 1 = transparency enabled Instruction Target Opcode 61hInstruction Target Opcode 45h Destination Transparency Mode See BR00 definitionFullblt Fullmonosrcblt Destination Transparency ColorInstruction Target Opcode 46h Instruction Target Opcode 47h Dword Length 09h181 Instruction Target Opcode 48h Dword Length 0Ah183 BLT Engine Instruction Definitions 12.3.1. BR00-BLT Opcode and Control185 SolPat Rsvd Mono 187 12.3.3. BR02-Clip Rectangle Y1 Address 12.3.4. BR03-Clip Rectangle Y2 Address12.3.5. BR04-Clip Rectangle X1 3128 Reserved. Must be Zero 271612.3.6. BR05-Setup Expansion Background Color 12.3.7. BR06-Setup Expansion Foreground Color12.3.8. BR07-Setup Color Pattern Address 12.3.9. BR08-Destination X1 12.3.10. BR09-Destination Address and Destination Y1 Address 12.3.11. BR10-Destination Y2 AddressSource Pitch Offset or Monochrome Source Quadwords 12.3.13. BR12-Source Address 12.3.14. BR13-BLT Raster OP, Control, and Destination Pitch Increment/Decrement SelectSource Select Mode Dynamic Color Depth12.3.15. BR14-Destination Width & Height 12.3.16. BR15-Color Pattern Address 12.3.18. BR17-Pattern Expansion Foreground Color 3124 Reserved. Must be Zero 23012.3.20. BR19-Source Expansion Foreground Color SSLADD-Source Scan Line Address DSLH-Destination Scan Line HeightDSLRADD-Destination Scan Line Read Address 204 Rendering Engine Instructions GfxprimitiveAxis Aligned Rectangles Primitive Winding OrderPrimitive Rendering Instruction Format Position MaskBias Variable Length Vertex Formats for Rendering Instructions Vertex Attribute CommentsGfxvertex Gfxrenderstatevertexformat Gfxblock Rendering Block 1EhBlock Type Block Pattern FormatPrediction Type DWord BitsVertical Motion Vector Precision 00 = 1/2 pixel 212 Precision Format Range Non-pipelined State VariablesMotion Vector Format Gfxrenderstatemaptexels Gfxrenderstatemapcoordsets Update Coordinate Set Index The valid range is Normalized Coordinate Set Mask 0 = Do not update 1 = UpdateOpcode 1h Normalized Coordinate SetGfxrenderstatemapinfo Discrete Integrated Base Utilize Fence Tiled Surface Walk3DstateMW 1Dh Dwordlength 2hReserved 0h Surface FormatColor Space Conversion Enable 1511221 Gfxrenderstatemapfilter Reserved 00h Mip Mode Filter Valid values are Opcode 2hGfxrenderstatemaplodlimits Opcode 3hOpcode 4h Texture LOD Dither Weight Mask 0 = Do not update 1 = UpdateGfxrenderstatemaplodcontrol Opcode 82h Gfxrenderstatemappaletteload3DStateMWNPNon-pipelined 1Dh Gfxrenderstatemapcolorblendstages Blend Equation DescriptionUpdate Blending Stage Index The valid range is 3DState24 00hWrite result to Current Register or Accumulator Select Replicate Arg1 Alpha to Color ChannelsInvert Color Arg2 Gfxrenderstatemapalphablendstages Invert Alpha Arg2 3DState24 01hInvert Alpha Arg1 Gfxrenderstatecolorfactor Instruction 1hKill Pixel Mode GfxrenderstatecolorchromakeyKeyedPixelControl KeyedPixelControl Write Mask 0 = Do not update 1 = UpdateInstruction 2h Monochrome Specular Full Color RGB GfxrenderstatesrcdstblendmonoNo Specular 236 Opcode Source / Destination Blend State 3DState24NP Non-pipelined 14h Alpha Reference State Mask 1 = Update 0 = Do Not UpdateGfxrenderstatezbiasalphafuncref Gfxrenderstatelinewidthcullshade Mode Alpha Shade Mode State Mask 1 = Update 0 = Do Not Update Specular Shade Mode State Mask 1 = Update 0 = Do Not UpdateColor Shade Mode State Mask 1 = Update 0 = Do Not Update 2824 3DState24 02hAlpha Setup Enable Enable Mask 1 = Update 0 = Do Not Update Color Index Key Enable Mask 1 = Update 0 = Do Not UpdateSpecular Enable State Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA1Specular Dither Enable Mask 1 = Update 0 = Do Not Update Frame Buffer Write Enable Mask 1 = Update 0 = Do Not UpdateBuffer Write Enable Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA23DState24NP Non-pipelined 15h GfxrenderstatefogcolorGfxrenderstatedrawingrectangleinfo 3DStateMWNP Non-pipelined 1Dh Opcode 80hGfxrenderstatescissorenable Scissor Rectangle Enable Mask 1 = Update 0 = Do Not Update3DState16NP Non-pipelined 1Ch Opcode 10hGfxrenderstatescissorrectangleinfo Opcode 81hStipple Pattern Stipple PatternOpcode 83h Gfxrenderstateantialiasing Gfxrenderstateprovokingvtxpixelization Rule Vertex SequenceSmall Triangle Filter Enable Mask Pixelization Rule MaskGfxrenderstatedestbuffervariables Opcode 85hDest Buffer Format 0h = Any 8-bit Surface Programming Hints/Rules Drawing and Scissor RectanglesColor Calculator 255 256 Clock Control Registers Programming NotesDCLK0D-Display Clock 0 Divisor Register Example Programming Sequence DCLK2DCLK1D-Display Clock 1 Divisor Register DCLK2D-Display Clock 2 Divisor Register LCDCLKD-LCD Clock Divisor Register Reserved VCO Loop Divide LCD Clock DCLK0DS-Display & LCD Clock Divisor Select RegisterPost Divisor Select LCD Clock Post Divisor Select clock VCO Loop Divide clockPWRCLKC-Power Management and Miscellaneous Clock Control Internal DAC EnableOverlay Registers Register/Instruction Category Comment15.1. OV0ADD-Overlay 0 Register Update Address Register Updating Register ValuesDOV0STA-Display/Overlay 0 Status Register Gamma Correction GAMC50-Gamma Correction RegistersRed Green BlueMathematical Gamma Correction For Overlay Three timesGamma Correction Theory Of Operation Latch AddressGamma Hardware Implementation Memory Offset Registers Overlay Buffer Pointer RegistersOBUF0Y-Overlay Buffer 0 Y Pointer Register Format AlignmentOBUF1Y-Overlay Buffer 1 Y Pointer Register OBUF0U-Overlay Buffer 0 U Pointer RegisterBit Descriptiont OBUF0V-Overlay Buffer 0 V Pointer RegisterOBUF1U-Overlay Buffer 1 U Pointer Register 15.4.2.1. OV0STRIDE-Overlay 0 Stride Register Overlay Stride RegistersOBUF1V-Overlay Buffer 1 V Pointer Register Overlay Initial Phase Registers YRGBVPH-Y/RGB Vertical Phase RegisterUVVPH-UV Vertical Phase Register HORZPH-Horizontal Phase RegisterINITPH-Initial Phase Register DWINSZ-Destination Window Size Register Overlay Destination Window Position/Size RegistersDWINPOS-Destination Window Position Register Overlay Source Size Registers SWID-Source Width RegisterSWIDQW-Source Width In QWords Register SHEIGHT-Source Height Register Overlay Scale Factor Registers YRGBSCALE-Y/RGB Scale Factor RegisterUVSCALE-UV Scale Factor Register 15.4.7.2. OV0CLRC1-Overlay 0 Color Correction 1 Register Overlay Color Correction Registers15.4.7.1. OV0CLRC0-Overlay 0 Color Correction 0 Register Overlay Destination Color Key Registers DCLRKV-Destination Color Key Value RegisterDCLRKM-Destination Color Key Mask Register Destination Constant Alpha Blend EnableAlways Constant Alpha Blend Enable Overlay Source Color Key Registers SCLRKVH-Source Color Key Value High RegisterSCLRKVL-Source Color Key Value Low Register SCLRKM-Source Color Key Mask RegisterSource Constant Alpha Blend Enable Overlay Configuration Registers 15.4.10.1. OV0CONF-Overlay Configuration Register15.4.11. OV0CMD-Overlay Command Register Vertical Chrominance Filter. Vertical Chrominance Filter Vertical Luminance Filter. Vertical Luminance FilterAutomatic flipping Manual flip commandSource Format 297 Overlay Alpha Blend Window Position/Size Registers AWINPOS-Alpha Blend Window Position RegisterOverlay Flip Instruction AWINSZ-Alpha Blend Window Size Register300 FENCE-Graphics Memory Fence Table Registers Instruction, Memory, and Interrupt Control RegistersInstruction Control Registers Reserved for address bits 31 downto Tile walkFence size Fence PitchPGTBLCTL-Page Table Control Register Normal Invalidation MechanismPGTBLER-Page Table Error Register Error Type PGTBLERRMSK-Page Table Error Mask Register Buffer Unit Page Table Error Mask Command Streamer DMA Page Table Error MaskOverlay Page Table Error Mask Display Page Table Error MaskRINGBUF-Ring Buffer Registers Intel 810 Chipset and Intel815 Chipset ErrataReserved Ring Buffer ValidHWSPGA-Hardware Status Page Address Register DWord Description OffsetIPEIR-Instruction Parser Error Identification Register debug IPEHR-Instruction Parser Error Header Register debugThis read only register reports engine done signals INSTDONE-Instruction Stream Interface Done RegisterNOPID-NOP Identification Register INSTPM-Instruction Parser Mode Register Disable State Variable UpdatesINSTPS-Instruction Parser State Register debug Cscpr State Machine Command Parser BBPPTR-Batch Buffer Parser Pointer Register debug ABBSTR-Active Batch Buffer Start Address Register debugCurrent DMA Address Reserved User of the DMA Engine ABBEND-Active Batch Buffer End Address Register debugDMAFADD-DMA Engine Fetch Address debug MEMMODE-Memory Interface Mode Register debug Reserved Host Graphics Prefetch ModeGraphics Address Translation Mode Instruction Fifo Debug ModeInterrupt Control Registers Bit Definition For Interrupt Control Registers321 HWSTAM-Hardware Status Mask Register IER-Interrupt Enable Register Interrupt Enables. See TableIIR-Interrupt Identity Register Interrupt Identity. See. TableIMR-Interrupt Mask Register Interrupt Mask Bits. See. TableISR-Interrupt Status Register Error Identity, Mask and Status Registers Table Error handling in Intel 815 ChipsetResetting the Page Table Error Table ErrorEIR-Error Identity Register EMR-Error Mask RegisterESR-Error Status Register Display Interface Control FWBLC-FIFO Watermark and Burst Length Control332 LCD / TV-Out Register Description HTOTAL-Horizontal Total RegisterHBLANK-Horizontal Blank Register HSYNC-Horizontal Sync Register VTOTAL-Vertical Total Register VBLANK-Vertical Blank Register VSYNC-Vertical Sync Register Sync Polarity Control LCD / TV-Out EnableLCDTVC-LCD/TV-Out Control Register FP Vesa VGA Mode FP / 740 Data OrderingFpvsync Control Fphsync ControlBorder Enable Fphsync Output ControlActive Data Order Active Data PolarityOVRACT-Overlay Active Register BCLRPAT- Border Color Pattern RegisterLocal Memory Interface DRT-DRAM Row TypeReserved Paging Mode Control PMC Bit RAS#-to-CAS# delay t RCDDRAMCL-DRAM Control Low Bit RAS# act. To precharge t RAS Refresh to RAS# act. t RCDRAMCH-DRAM Control High 346 HSYNC/VSYNC Control1916 19. I/O Control RegistersHVSYNC-HSYNC/VSYNC Control Register Gpio Registers GPIOAGeneral Purpose I/O Control Register aValue .bit GPIOBGeneral Purpose I/O Control Register B 351 352 Line Counter for Display Display And Cursor RegistersDISPSL-Display Scan Line Count DISPSLC-Display Scan Line Count Range Compare Inclusive / ExclusivePIXCONF-Pixel Pipeline Configuration Reserved Display path Graphics Gamma Enable. See noteOverlay path Gamma Enable. See note Pixel Pipeline ControlDisplay Color Mode Bit DAC EnableEnable Extended Status Read Mode CRT Overscan ColorGUI Mode Transition from VGA modes to hires mode or oppositeBLTCNTL-BLT Control SWF13-Software Flag RegistersDPLYBASE-Display Base Address Register Reserved Flat Panel Hot Plug Detect Enable Vertical Sync Status EnableDisplay Line Compare Enable DPLYSTAS-Display Status Select RegisterVertical Blank Enable Overlay Registers Upated EnableOverlay Registers Updated Status Vertical Sync StatusReserved Cursor Coordinate System Origin Select Hardware CursorCURCNTR-Cursor Control Register CURBASE-Cursor Base Address Register CURPOS-Cursor Position RegisterAppendix a Mode Parameters Parameters for Screen Resolution/Refresh Rate 320x20070Hz = Parameters for Screen Resolution/Refresh Rate 320x24070Hz = Parameters for Screen Resolution/Refresh Rate 352X48070Hz = Parameters for Screen Resolution/Refresh Rate 352X57670Hz = Parameters for Screen Resolution/Refresh Rate 400x30070Hz = Parameters for Screen Resolution/Refresh Rate 512X38470Hz = Parameters for Screen Resolution/Refresh Rate 640x35085Hz = Parameters for Screen Resolution/Refresh Rate 640x40070Hz = Parameters for Screen Resolution/Refresh Rate 640x40085Hz = Parameters for Screen Resolution/Refresh Rate 640x48060Hz = Parameters for Screen Resolution/Refresh Rate 640x48070Hz = Parameters for Screen Resolution/Refresh Rate 640x48072Hz = Parameters for Screen Resolution/Refresh Rate 640x48075Hz = Parameters for Screen Resolution/Refresh Rate 640x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x40085Hz = Parameters for Screen Resolution/Refresh Rate 720x48060Hz = Parameters for Screen Resolution/Refresh Rate 720x48075Hz = Parameters for Screen Resolution/Refresh Rate 720x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x57660Hz = Parameters for Screen Resolution/Refresh Rate 720x57675Hz = Parameters for Screen Resolution/Refresh Rate 720x57685Hz = Parameters for Screen Resolution/Refresh Rate 800x60056Hz = Parameters for Screen Resolution/Refresh Rate 800x60060Hz = Parameters for Screen Resolution/Refresh Rate 800x60070Hz = Parameters for Screen Resolution/Refresh Rate 800x60072Hz = Parameters for Screen Resolution/Refresh Rate 800x60075Hz = Parameters for Screen Resolution/Refresh Rate 800x60085Hz = Parameters for Screen Resolution/Refresh Rate 854X48060Hz = Parameters for Screen Resolution/Refresh Rate 854X48075Hz = Parameters for Screen Resolution/Refresh Rate 854X48085Hz = 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 Intel around the world