Intel 815 manual IPEIR-Instruction Parser Error Identification Register debug

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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16.1.7.IPEIR—Instruction Parser Error Identification Register (debug)

Address Offset:	02088h
Default Value:	0000h
Access:	Read Only
Size:	32 bits

This register is used to help identify the instruction packet that generates an invalid instruction interrupt to the processor. The IPEIR will contain the origin of the offending packet. The Header will be stored in the error header register.

31	3	2	1	0
	Reserved	BATCH /		RING ID
		RING
Bit	Description
31:3	Reserved
2	BATCH / RING. The invalid instruction came from either a batch buffer or instruction ring.
	1 = Batch buffer
	0 = Instruction RING
1:0	RING ID. The invalid instruction came from the Low Priority (00) or the Interrupt (01) ring. If the invalid
	instruction came from a batch buffer, this bit identifies which Instruction Ring the batch buffer
	instruction came from.
	00 = Low Priority
	01 = Intr ring
	1X = Reserved

16.1.8.IPEHR—Instruction Parser Error Header Register (debug)

Address Offset:	0208Ch
Default Value:	0000h
Access:	Read Only
Size:	32 bits

This register is used to identify the instruction packet that generates an invalid instruction interrupt to the processor. The IPEHR will contain the header word of the offending packet. For debug purposes, the header of all instructions parsed will be written to this register. If an error occurs, the instruction parser halts. An interrupt indicating an error will be generated if it is unmasked.

Bit	Description
31:0	Header. This field will contain the instruction Header field of the instruction packet that generates an
	invalid instruction interrupt.

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