Intel 815 manual Graphics Translation Table GTT Range Definition

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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4.Graphics Translation Table (GTT) Range Definition

Address Offset:	10000h–FFFFh
Default Value:	Page table range 64 KB
Access:	aligned DWord-QWord Write Only

This range defined within the graphics memory mapped register space is for the memory manager to access the graphics translation table. A page table write will invalidate that entry in internal translation table caches (TLBs). The translation table resided in system memory and can be accessed by the memory manager directly. However, to ensure coherency between hardware maintained translation caches and the translation table in main memory, the memory manager must use this range to update the translation table.

The page table is required to be QW aligned with each entry being DWord aligned such that each QW stores the translation for 2, 4 KB pages. Page Table base address for graphics memory is programmed in the PGTB_CNTL register. For graphics memory of 64 MB with a TLB block size of 4 KB, 16K entries are needed. Each entry is 4 bytes; hence, the page table size is 64 KB.

Page Table Entry: 1 DWord per 4-KB page.

31	30	29	12	11	3	2	1	0
XX=00		Physical Address 29:12		Reserved		T1T0		V

V:1 = Valid page table entry (PTE).

0 = Invalid page table entry (PTE). An access to an invalid PTE will result in an interrupt.

T1T0:	01	= Physical address targets Local Memory
	00	= Physical address targets main memory (not snooped)
	11	= Physical address targets cacheable main memory (results in snoop on processor bus)
	10	= Reserved.

Note: T1T0 = 11 is used only if the surface is a Blit soure or destination operand used within the context of a source copy command.

Note that the 4-KB pages of physical main memory (that have been mapped to the graphics aperture through the GTT) must be accessed strictly through the aperture. The GMCH does not guarantee data coherency if any of these pages are accessed directly using their physical addresses. For example, a 4-KB page of main memory has been mapped via the GTT to a 4-KB aperture page. Although, the GMCH still allows this 4-KB page to be accessed directly through its physical memory address, the chipset does not guarantee data coherency with respect to accesses through the normal graphics aperture address range. This is because a read to the aperture memory can result in prefetching and caching of data, while a write to the aperture can result in temporary write data buffering in the graphics controller of the GMCH. Accesses to these same memory locations through their physical address take a different logical path through the chipset controller side of the GMCH. There is no hardware support for ensuring coherency between these two access paths.

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