Intel 815 manual Clock Control Registers, Programming Notes

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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14.Clock Control Registers

The clock control registers are accessed by writing to the memory mapped address offset.

The Intel® 815 chipset has three PLLs to generate all the clocks. The Host PLL generates the host clock whose frequency is controlled by an external strap. In addition, the Host PLL generates the system and local memory core clock and graphics core clock. The Hub PLL generates the clock for the Hub Interface unit. The Display PLL generates the display or LCD clock.

The display clock can be controlled by three blocks of registers: DCLK0, DCLK1, and DCLK2. Each display clock has its own Display Clock i Divisor registers for M, N and a byte of Display & LCD Clock Divisor Select Register within which are P (Divisor) values and can be programmed independently. DCLK0 and DCLK1 normally are programmed to 25.175 MHz and 28.322 MHz respectively (VGA compatible clocks), DCLK2 is used for non-VGA modes.

The Display Clock i Divisor register and the appropriate byte of Display & LCD Clock Divisor Select Register are programmed with the loop parameters to be loaded into the clock synthesizer. The MSR[3:2] register is used to select between DCLK0(default), DCLK1 and DCLK2. Writing to LCD / TV-Out Control [31] = 1 and [0] = 1 selects the LCD clock. The MSR[3:2] are ignored when this condition is true.

The data written to these registers are calculated based on the reference frequency, the desired output frequency, and characteristic VCO constraints as described in the Functional Description. From the calculation, the M,N and P values are obtained.

14.1.Programming Notes

Three blocks of registers exist to program up to three unique frequencies for the display clock. These registers are named DCLK0, DCLK1, and DCLK2. Each of these blocks can be programmed independently of each other. However, only one can be used to control the DPLL at any given time.

The MSR register (bits 3:2) is used to determine which of the DCLK0, 1, 2 registers groups will control the DPLL. Writing to the MSR register bits 3:2 also transfers the Display Clock Divisor and Display & LCD Clock Divisor Select Register contents to the VCO register file.

Example Programming Sequence (DCLK0)

1.Write the Display Clock 0 Divisor register with the M-REG value and N-REG value.

2.Write the clock 0 byte of the Display & LCD Clock Divisor Select Register with the P-REG value.

3.Write the MSR register, bits 3:2 = '00', to select DCLK0 (NOTE: This is the default value).

Example Programming Sequence (DCLK1)

1.Write the Display Clock 1 Divisor register with the M-REG value and N-REG value.

2.Write the clock 1 byte of the Display & LCD Clock Divisor Select Register with the P-REG value.

3.Write the MSR register, bits 3:2 = '01', to select DCLK1.

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