Intel 815 manual 15. CR0DStart Address Low Register, 16. CR0EText Cursor Location High Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.6.15.CR0DStart Address Low Register

I/O (and Memory Offset) Address:			3B5h/3D5h (index=0Dh)
Default:			Undefined
Attributes:			Read/Write
	Bit		Description
	7:0	Start Address Bits [7:0] or [9:2]. This register provides either bits 7 through 0 of a 16 bit value that
		specifies the memory address offset from the beginning of the frame buffer, or bits 9 through 2 of a 32 bit
		buffer address at which the data to be shown in the active display area begins. (default is 0)
		In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the start address is
		specified with a 16-bit value. The eight bits of the Start Address High Register (CR0C) provide the eight
		most significant bits of this value, while the eight bits of this register provide the eight least significant
		bits.
		In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the start address is
		specified with a 32-bit value. Bits 31 through 24 of this value are provided by the Extended Start
		Address High Register (CR42). Bits 23 through 18 of this value are provided by bits 5 through 0 of the
		Extended Start Address Register (CR40). Bits 17 through 10 of this value are provided by the Start
		Address High Register (CR0C). Bits 9 through 2 of this value are provided by this register. Bits 1 and 0
		of this value are always 0, and therefore not provided. It should be further noted that, in extended
		modes, these 32 bits from these four registers are double-buffered and synchronized to VSYNC to
		ensure that changes occurring on the screen as a result of changes in the start address always have a
		smooth or instantaneous appearance. To change the start address in extended modes, all three
		registers must be set for the new value, and then bit 7 of the Extended Start Address Register (CR40)
		must be set to 1. Only if this is done, will the hardware update the start address on the next VSYNC.
		When this update has been performed, the hardware will set bit 7 of the Extended Start Address
		Register (CR40) back to 0.

9.6.16.CR0EText Cursor Location High Register

I/O (and Memory Offset) Address:	3B5h/3D5h (index=0Eh)
Default:	Undefined
Attributes:	Read/Write

This cursor is the text cursor that is part of the VGA standard, and should not be confused with the hardware cursor and popup (a.k.a., cursor and cursor 2), which are intended to be used in graphics modes. This text cursor exists only in text modes, and so this register is entirely ignored in graphics modes.

Bit	Description
7:0	Text Cursor Location Bits [15:8]. This field provides the 8 most significant bits of a 16-bit value that
	specifies the address offset from the beginning of the frame buffer at which the text cursor is located.
	Bits 7:0 of the Text Cursor Location Low Register (CR0F) provide the 8 least significant bits.

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