Intel manual Host Interface, Intel 82815 Chipset Gmch Block Diagram

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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•Support for a single processor configuration

•64-bit AGTL+ based System Bus Interface at 66/100/133 MHz

•32-bit Host Address Support

•64-bit System Memory Interface with optimized support for SDRAM at 100/133 MHz

•Integrated 2D & 3D Graphics Engines

•Integrated H/W Motion Compensation Engine

•Integrated 230 MHz DAC

•Integrated Digital Video Out Port

•133 MHz Display Cache

•AGP 1X/2X/4X Controller

Figure 2. Intel® 82815 Chipset GMCH Block Diagram

				System Bus Interface
	Display Engine		3D Engine	Buffer
	HW Motion Comp		3D
Analog			Engine
	DAC	Overlay
Display			2D Engine
Out	HW Cursor
			Stretch	Memory Interface	System
			BLT Eng		Memory
Digital
	Digital Video Out		BLT Eng
Video
		Port
Out
DDC/
I2C			AGP Interface
AGP/				Buffer
Display
Cache	Local Memory			Hub Interface
Pins	Interface
					gmch_blk2.vsd

2.2.1.Host Interface

The host interface of the GMCH is optimized to support the Intel Pentium® III processor and Intel CeleronTM processor in the FC-PGA package. The GMCH implements the host address, control, and data bus interfaces within a single device. The GMCH supports a 4-deep in-order queue (i.e., supports pipelining of up to 4 outstanding transaction requests on the host bus). Host bus addresses are decoded by the GMCH for accesses to system memory, PCI memory and PCI I/O (via hub interface), PCI configuration space and Graphics memory. The GMCH takes advantage of the pipelined addressing capability of the processor to improve the overall system performance.

The Intel® 82815 chipset GMCH supports the 370-pin socket processor.

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