Intel 815 manual Odd/Even Mode, Read Mode, Write Mode

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

Bit Description

4Odd/Even Mode.

0 = Addresses sequentially access data within a bit map, and the choice of which map is accessed is made according to the value of the Plane Mask Register (SR02).

1 = The frame buffer is mapped in such a way that the function of address bit 0 is such that even addresses select memory planes 0 and 2 and odd addresses select memory planes 1 and 3.

Note:

This works in a way that is the inverse of (and is normally set to be the opposite of) bit 2 of the Memory Mode Register (SR02).

3Read Mode.

0 = During a processor read from the frame buffer, the value returned to the processor is data from the memory plane selected by bits 1 and 0 of the Read Plane Select Register (GR04).

1 = During a processor read from the frame buffer, all 8 bits of the byte in each of the 4 memory planes corresponding to the address from which a processor read access is being performed are compared to the corresponding bits in this register (if the corresponding bit in the Color Don’t Care Register (GR07) is set to 1). The value that the processor receives from the read access is an 8-bit value that shows the result of this comparison. A value of 1 in a given bit position indicates that all of the corresponding bits in the bytes across all 4 of the memory planes that were included in the comparison had the same value as their memory plane’s respective bits in this register.

2Reserved. Read as 0s.

1:0 Write Mode.

00 = Write Mode 0  During a processor write to the frame buffer, the addressed byte in each of the 4 memory planes is written with the processor write data after it has been rotated by the number of counts specified in the Data Rotate Register (GR03). If, however, the bit(s) in the Enable Set/Reset Register (GR01) corresponding to one or more of the memory planes is set to 1, then those memory planes will be written to with the data stored in the corresponding bits in the Set/Reset Register (GR00).

01 = Write Mode 1  During a processor write to the frame buffer, the addressed byte in each of the 4 memory planes is written to with the data stored in the memory read latches. (The memory read latches stores an unaltered copy of the data last read from any location in the frame buffer.)

10 = Write Mode 2  During a processor write to the frame buffer, the least significant 4 data bits of the processor write data is treated as the color value for the pixels in the addressed byte in all 4 memory planes. The 8 bits of the Bit Mask Register (GR08) are used to selectively enable or disable the ability to write to the corresponding bit in each of the 4 memory planes that correspond to a given pixel. A setting of 0 in a bit in the Bit Mask Register at a given bit position causes the bits in the corresponding bit positions in the addressed byte in all 4 memory planes to be written with value of their counterparts in the memory read latches. A setting of 1 in a Bit Mask Register at a given bit position causes the bits in the corresponding bit positions in the addressed byte in all 4 memory planes to be written with the 4 bits taken from the processor write data to thereby cause the pixel corresponding to these bits to be set to the color value.

11 = Write Mode 3  During a processor write to the frame buffer, the processor write data is logically ANDed with the contents of the Bit Mask Register (GR08). The result of this ANDing is treated as the bit mask used in writing the contents of the Set/Reset Register (GR00) are written to addressed byte in all 4 memory planes.

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