Intel 815 manual Graphics Address Translation

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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3.4.1.Graphics Address Translation

The Intel® 815 chipset uses a logical memory-addressing concept for accessing graphics data. The GC supports a 64-MB logical address space, where each 4-KB logical page can be mapped to a physical memory page in System RAM, PCI Memory, or an optional Display Cache memory. This mapping is performed through the use of a Graphics Translation Table (GTT).

GC engines can address the full 64-MB logical address space. The processor is provided access to either the full 64-MB space, or just the lower 32 MB, via a PCI memory range associated with the graphics device.

The GTT is allocated in system RAM and maintained by the graphics driver. The 4 KB-aligned physical address of the 64 KB GTT is programmed via the GC’s PGTBL register.

Each of the 16K DWord GTT entries can map a 4-KB logical page to a physical memory page. Fields in the GTT entry control the mapping of that logical page in the following manner:

•(V) whether or not that logical 4 KB page is mapped to a physical memory page. Accesses to invalid pages will result in an error interrupt.

•(T1T0) the physical memory address space of the mapped page:

System RAM page (no processor cache snoop)

PCI Memory page (processor cache snooped if below TOM)

Display Cache page

•the page number of the mapped page (within the particular physical memory address space)

Although the GTT format permits any logical page to be mapped to any page in the supported physical memory address spaces, the GC imposes restrictions on how specific graphics operands (buffers, etc.) can be mapped to physical memory.

The GTT entries must be written via a GTT alias in the graphics device’s memory-mapped register space (10000h–1FFFFh). This allows the GC to snoop GTT entry writes and invalidate graphics TLBs as required. The GTT entries must not be written directly in system memory.

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