Intel 815 manual 4. SR02Plane/Map Mask

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

9.2.4.SR02Plane/Map Mask

I/O (and Memory Offset) Address:			3C5h (Index=02h)
Default:			00h
Attributes:			Read/Write
7			4	3	0
		Reserved		Memory Planes Processor Write Access Enable.
	Bit		Descriptions
7:4		Reserved. Read as 0s.
3:0		Memory Planes [3:0] Processor Write Access Enable. In both the Odd/Even Mode and the Chain 4
		Mode, these bits still control access to the corresponding color plane.
		0 = Disable.
		1 = Enable.

Note:

This register is referred to in the VGA standard as the Map Mask Register. However, the word “map” is used with multiple meanings in the VGA standard and was, therefore, considered too confusing; hence, the reason for calling it the Plane Mask Register.

87