Intel 815 manual 115

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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Bit Description

6Vertical Display Enable End Bit 9. The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the last scan line within the active display area.

In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical display enable end is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the Vertical Display Enable End Register (CR12), and the most and second-most significant bits are supplied by this bit and bit 1, respectively, of this register.

In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical display enable end is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the Vertical Display Enable End Register (CR12), and the 4 most significant bits are supplied by bits [3:0] of the Extended Vertical Display End Enable Register (CR31). In extended modes, neither this bit, nor bit 1 of this register are used.

This 10-bit or 12-bit value should be programmed to be equal to the number of the last scan line within in the active display area. Since the active display area always starts on the 0th scan line, this number should be equal to the total number of scan lines within the active display area, minus 1.

5Vertical Total Bit 9. The vertical total is a 10-bit or 12-bit value that specifies the total number of scan lines. This includes the scan lines both inside and outside of the active display area.

In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical total is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the Vertical Total Register (CR06), and the most and second-most significant bits are supplied by this bit and bit 0, respectively, of this register.

In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical total is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the Vertical Total Register (CR06), and the 4 most significant bits are supplied by [3:0] bits of the Extended Vertical Total Register (CR30). In extended modes, neither this bit, nor bit 0 of this register are used.

This 10-bit or 12-bit value should be programmed equal to the total number of scan lines, minus 2.

4Line Compare Bit 8. This bit provides the second most significant bit of a 10-bit value that specifies the scan line at which the memory address counter restarts at the value of 0. Bit 6 of the Maximum Scan Line Register (CR09) supplies the most significant bit, and bits 7-0 of the Line Compare Register (CR18) supply the 8 least significant bits.

Normally, this 10-bit value is set to specify a scan line after the last scan line of the active display area. When this 10-bit value is set to specify a scan line within the active display area, it causes that scan line and all subsequent scan lines in the active display area to display video data starting at the very first byte of the frame buffer. The result is what appears to be a screen split into a top and bottom part, with the image in the top part being repeated in the bottom part.

When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low Register (CR0D), it is possible to create a split display, as described earlier, but with the top and bottom parts displaying different data. The top part will display what data exists in the frame buffer starting at the address specified in the two aforementioned start address registers, while the bottom part will display what data exists in the frame buffer starting at the first byte of the frame buffer.

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