Intel 815 manual 321

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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Bit		Description
9	Overlay 0 Flip Pending. Status bit is set to reflect a pending flip when the parser parses a flip packet
	and cleared when the flip takes place (Display VBLANK), whereas IIR reflects Flip-Occurred# (which is
	contrary to the general definition of setting of IIR bits when interrupts occur). This is only affected by
	the use of flip packets not through the manual method or the capture auto flipping. To prevent race
	conditions, status register write must occur before the STOREDWORD following the flip packet is
	written.
8	Reserved
7	Primary Display VBLANK. Set at leading edge of display VBLANK. This is actually delayed to allow
	all internal hardware VBLANK events to occur before the interrupt is generated to eliminate race
	conditions. These events include the update of the display and overlay status bits and loading of the
	overlay registers.
6	Primary Display Event. Interrupt cause will be determined by reading the display status register and
	is one of the following:
	•	Flat Panel Hot Plug Detect Interrupt
	•	Display VSYNC
	•	Display Line Compare
	On active going edge of OR of unmasked Display event bits
	Status - OR of unmasked Display event bits
	Note that the display line compare is also used through the instruction parser packet interface.
5	Reserved
4	Reserved
3	Reserved
2	Reserved
1	User Defined Interrupt. The Instruction Parser passed a “user-defined interrupt” packet. This is
	intended to be used with another mechanism (e.g., STOREDW instruction) to determine the source of
	the packet.
0	Breakpoint. The Instruction Parser parsed a “breakpoint” interrupt packet. The
	GFXCMDPARSER_BREAKPOINT_INTERRUPT packet can be used to generate a store dword cycle
	from the command streamer to main memory and halt the parsing of further commands. The
	HWSTAM (Hardware Status Mask Register- Offset 02098h) must have the break point bit unmasked
	to generate the store dword. In addition to the HWSTAM register, the corresponding bit in the IMR
	(Interrupt Mask Register - Offset 020A8h) must also be unmasked to halt the parsing of further
	commands. At the break point command packet , if both the HWSTAM and IMR are unmasked, the
	command parser will stop processing further commands until the breakpoint bit in the IIR (Interrupt
	Identity Register - Offset 020A4h) is cleared.

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