NTAK09 1.5 Mb DTI/PRI card Page 707 of 894
Circuit Card Description and Installation
Clock controller interface
The clock controller interface provides the recovered clock from the external
digital facility to the clock controller daughterboard through the backplane.
Depending on the equipped state of the clock controller, the clock controller
interface enables or disables the appropriate reference clock source, in
conjunction with software.
Note: Clocking slips can occur between MG 1000S systems that are
clocked from different Central Offices (COs), if the COs are not
synchronized. The slips can degrade voice quality.

Clock rate converter

The 1.5 Mb clock is generated by a Phase-Locked Loop (PLL). The PLL
synchronizes the 1.5 Mb DS1 clock to the 2.56 Mb system clock through the
common multiple of 8 kHz by using the main frame synchronization signal.
pin 49 pin 3 T1 receive tip from network
pin 24 pin 11 R1 receive ring from network
IMPORTANT!
Each MG 1000S that has a digital trunk must have a clock controller
clocked to an external reference clock.
Table 228
DS-1 line interface pinout for NTBK04 cable (Part 2 of 2)
From 50-pin MDF
connector To DB-15 Signal name Description