Nortel Networks 553-3001-211 High-Level Data Link Controller Hdlc, CPU to Misp bus interface

NTBK22 MISP card Page 759 of 894

High-Level Data Link Controller (HDLC)

The HDLC is a format converter that supports up to 32 serial channels that communicate at speeds up to 64 kbps. The HDLC converts messages into the following two message formats:

•a serially transmitted, zero-inserted, CRC protected message that has a starting and an ending flag

•a data structure

CPU to MISP bus interface

Information exchange between the CPU and the MISP is performed with packetized messages transmitted over the CPU bus. This interface has a 16-bit data bus, an 18-bit address bus, and interrupt and read/write control lines.

This interface uses shared Static Random Access Memory (SRAM) as a communication exchange center between the CPU and the MPU. Both the CPU and the MPU can access this memory over the transmit and receive channels on the bus.

MISP network bus interface

The network bus interface:

•converts bit interleaved serial data received from the network bus into byte interleaved data for transmission over the 32 time slots used by the HDLC controller

•accepts byte interleaved data transmitted from the HDLC controller and converts it into a bit interleaved data stream for transmission over the network bus

Power consumption

Power consumption is +5V at 2 A; +15V at 50 mA; and -15V at 50 mA.

Circuit Card Description and Installation