Nortel Networks 553-3001-211 manual IPE interface logic, Interface logic

Page 370 of 894 NT6D70 SILC Line card

The reset and sanity timer logic resets the MCU.

The serial control interface is an IPE bus used by the MPU to communicate with the S/T transceivers.

IPE interface logic

The IPE interface logic consists of a Card-LAN interface, an IPE bus interface, a maintenance signaling channel interface, a digital pad, and a clock controller and converter.

The Card-LAN interface is used for routine card maintenance, which includes polling the line cards to find the card slot where the SILC is installed. It also queries the status and identification of the card and reports the configuration data and firmware version of the card.

The IPE bus interface connects an IPE bus loop that has 32 channels operating at 64 kbps and one additional validation and signaling bit.

The Maintenance Signaling Channel (MSC) interface communicates signaling and card identification information from the system CPU to the SILC MCU. The signaling information also contains maintenance instructions.

The digital pad provides gain or attenuation values to condition the level of the digitized transmission signal according to the network loss plan. This sets transmission levels for the B-channel voice calls.

The clock recovery circuit recovers the clock from the local exchange.

The clock converter converts the 5.12-MHz clock from the IPE backplane into a 2.56 MHz clock to time the IPE bus channels and an 8 kHz clock to provide PCM framing bits.

S/T interface logic

The S/T interface logic consists of a transceiver circuit and the DSL power source. This interface supports DSLs of different distances and different numbers and types of terminal.

553-3001-211 Standard 2.00 September 2004