Nortel Networks 553-3001-211 manual Phase difference detector circuit, Digital phase lock loops

NTAK20 Clock Controller daughterboard Page 727 of 894

Functional description

The main functional blocks of the NTAK20 architecture include:

•phase difference detector circuit

•digital Phase Locked Loop (PLL)

•clock detection circuit

•digital-to-analog converter

•CPU MUX bus interface

•signal conditioning drivers and buffers

•sanity timer

•microprocessor

•CPU interface

•external timing interface

Phase difference detector circuit

This circuit, under firmware control, enables a phase difference measurement to be taken between the reference entering the PLL and the system clock.

The phase difference is used for making frequency measurements and evaluating input jitter and PLL performance.

Digital phase lock loops

The main digital PLL enables the clock controller to provide a system clock to the CPU. This clock is both phase and frequency locked to a known incoming reference.

The hardware has a locking range of + 4.6 ppm for Stratum 3 and + 50 ppm for Stratum 4 (CCITT).

A second PLL on the clock controller provides the means for monitoring another reference. Note that the error signal of this PLL is routed to the phase difference detector circuit so the microprocessor can process it.

Circuit Card Description and Installation