Delta Electronics VFD-VL manual Division Factor, Leads B Leads a A/O B/O

Models: VFD-VL

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Appendix B Accessories

4. Output Signal Setting of the Frequency Divider

It generates the output signal of division factor “n” after dealing with the input pulse. Please set by the switch SW1 on the card.

 

RESERVE I/MODE O/MODE RST

 

BIT0 BIT1

 

BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

 

 

 

 

 

 

 

 

 

 

 

 

 

Division Factor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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ON

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

2

3

 

4

5

 

6

7

8

9

10 11 12

RESERVE: reserved bit (PIN1)

I/MODE: input type setting of the division pulse (PIN 2)

O/MODE: output type setting of the division pulse (PIN 3)

RST: clock reset bit (PIN 4)

Division factor: setting for division factor n: 1~256 (PIN5~12)

Settings and explanations

RESERVE

I/MODE

O/MODE

RST

 

Division factor

A leads B

B leads A

 

 

 

 

 

 

A-/A

A-/A

X

0

0

1

B-/B

B-/B

A/O-/A/O

A/O-/A/O

 

 

 

 

 

 

 

 

B/O-/B/O

B/O-/B/O

 

 

 

 

A-/A

A-/A

X

0

1

1

B-/B

B-/B

 

 

 

 

 

 

A/O-/A/O

A/O-/A/O

 

 

 

 

B/O-/B/O

B/O-/B/O

 

 

 

 

A-/A

A-/A

X

1

X

1

B-/B

B-/B

 

 

 

 

A/O-/A/O

A/O-/A/O

 

 

 

 

B/O-/B/O

B/O-/B/O

Revision Nov. 2008, VLE1, SW V1.03

B-27

Page 224
Image 224
Delta Electronics VFD-VL manual Division Factor, Leads B Leads a A/O B/O