Delta Electronics VFD-VL manual Division factor, Leads B Leads a

Models: VFD-VL

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Appendix B Accessories

Settings and explanations

RESERVE

I/MODE

O/MODE

RST

 

Division factor

A leads B

B leads A

 

 

 

 

 

A

 

A

 

 

 

B

 

B

X

0

0

1

 

 

 

 

 

A/O-/A/O

 

A/O-/A/O

 

 

 

B/O-/B/O

 

B/O-/B/O

 

 

 

A

 

A

X

0

1

B

 

B

1

 

 

 

 

 

A/O-/A/O

 

A/O-/A/O

 

 

 

B/O-/B/O

 

B/O-/B/O

X

1

X

1

This setting is NOT for EMVL-PGH01

NOTE

„When the switch is ON, it means logic 0.

„A-/A and B-/B are the input signals of PG card. A/O-/A/O and B/O-/B/O are the line drivers of the frequency divider measured by the differential probe.

„PIN1 is reserved.

„PIN 5~12 are the denominator for the frequency divider. PIN 5 is the low bit (EX: the setting of XXXX10101010 is that the input signal divides by 85).

„When PIN 2 and PIN 3 are set to 0, the input signals (A-/A and B-/B) of PG card should be square wave and A/O-/A/O and B/O-/B/O are the outputs of frequency divider.

„When PIN 2 is set to 0 and PIN 3 is set to 1, the input signals (A-/A and B-/B) of PG card should be square wave and B/O-/B/O is the indication of phase A and B. (EX: LOW means A leads B and HIGH means B leads A). A/O-/A/O is the output of frequency divider.

„When PIN 2 is set to 1 and PIN 3 is set to X, B-/B should be the input signal of direction indication. (EX: when B-/B is LOW, it means that A leads B. When B-/B is HIGH, it means

Revision Nov. 2008, VLE1, SW V1.03

B-31

Page 228
Image 228
Delta Electronics VFD-VL manual Division factor, Leads B Leads a