Agilent Technologies 35670-90066 manual Fast BUS

	Internal Test Descriptions	Agilent 35670A
	Self-Test Descriptions
[ DISTORTN ]	This test checks for noise and distortion in the input circuits of the A1 Input assembly or A2
	Input assemblies. In this test, the A5 Analog assembly’s source outputs a signal that is
	connected to the input channels via the calibration path (CALP). For each channel in the A1
	Input assembly, the signal is measured at 16.640 kHz for 5 Vpk ±0.5 Vpk and from 24.96 kHz
	to 51.2 kHz for 0 Vpk ±0.01V. For each channel in the A2 Input assemblies, the signal is
	measured at 8.320 kHz for 5 Vpk ±0.5 Vpk and from 12.48 kHz to 25.6 kHz for 0 Vpk ±0.01V.
[ FAST BUS ]	This test verifies that the fast bus is operating correctly. In this test, the microprocessor on the
	A7 CPU assembly writes data to the trigger gate array and digital tach on the A6 Digital
	assembly over the fast bus. The microprocessor then reads the data.
[ FIFO ]	This test verifies that the FIFO gate array on the A6 Digital assembly is operating correctly. In
	this test, the A7 CPU assembly’s microprocessor configures the FIFO gate array. The
	microprocessor then reads the control lines to check circuits internal to the gate array and verify
	correct configuration. The Trigger Gate Array [ TRIGGER ], Digital Filter Gate Array
	[ FILTER ], and LO Gate Array [ LO ] tests must pass for this test to pass. No data paths on
	the Digital assembly are checked.
[ FRONT PANEL ]	This test verifies that the IIC controller on the A11 Keyboard Controller assembly is operating
	correctly. In this test, the microprocessor on the A7 CPU assembly reads the IIC controller on
	the Keyboard Controller assembly and verifies that no front-panel keys are held down.
[ GPIB CONNECTOR ] This test was not implemented.
[ GPIB FUNC TEST ]	This test verifies that the GPIB interface on the A10 Rear Panel assembly is operating
	correctly. In this test, the A7 CPU assembly’s microprocessor sets the GPIB interface to a
	listen only state, then tests for a listen only state.
[ IIC BUS ]	This test verifies that the A7 CPU assembly can write to and read from all assemblies with IIC
	interfaces. This test also checks the A7 CPU assembly’s EEROM. The following assemblies
	have IIC interfaces:
	A1 Input
	A2 Input
	A5 Analog
	A6 Digital
	A8 Memory
	A10 Rear Panel
	A11 Keyboard Controller
[ INPUT A-WEIGHT ]	This test verifies that the A-weight filters on the A1 Input assembly or A2 Input assemblies are
	operating correctly. In this test, the A5 Analog assembly’s source outputs a chirp signal that is
	connected to the input channels via the calibration path (CALP). For each channel, the power
	spectrum is measured at three frequencies with and without the A-weight filter in the input
	path.
[ INPUT ICP ]	This test verifies that the ICP sources on the A1 Input assembly or A2 Input assemblies are
	operating correctly. In this test, the ICP sources are turned on, then measured for 25 ±10 Vdc.
	During this test, the front panel input BNC connectors must not be connected to anything.

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