Agilent 35670A

Internal Test Descriptions

 

Self-Test Descriptions

 

Individual Self-Test Descriptions

[ AAF BYPASS ]

This test verifies that the anti-alias filters and the bypass circuits on the A1 Input assembly or

 

A2 Input assemblies are operating correctly. In this test, the A5 Analog assembly’s source

 

outputs a signal that is connected to the input channels via the calibration path (CALP). For the

 

A1 Input assembly’s channel 1, power spectrum measurements are made with the signal routed

 

through the 100 kHz anti-alias filter, the 50 kHz anti-alias filter, and the bypass circuit. For the

 

A1 Input assembly’s channel 2, power spectrum measurements are made with the signal routed

 

through the 50 kHz anti-alias filter and the bypass circuit. For the A2 Input assembly’s channel

 

1 or 2, power spectrum measurements are made with the signal routed through the 50 kHz

 

anti-alias filter, the 25 kHz anti-alias filter, and the bypass circuit. For the A2 Input assembly’s

 

channel 3 or 4, power spectrum measurements are made with the signal routed through the

 

25 kHz anti-alias filter and the bypass circuit.

[ ADC GATE ARRAY ] This test verifies that the A5 Analog assembly’s ADC gate array is functioning correctly. This

 

test consists of 7 tests — positive overflow, negative overflow, positive limit, negative limit,

 

1st pass, 2nd pass, and zero. The positive and negative overflow tests set up the ADC test

 

mode to cause positive and negative overflows, then check the A6 Digital assembly’s digital

 

filter for interrupt flags. The positive and negative limit tests check the ADC’s positive and

 

negative limits. The 1st and 2nd pass tests connect the calibration signal from the A5 Analog

 

assembly to the A1 Input assembly or A2 Input assemblies. The 1st pass test sets the 2nd pass

 

result to zero and checks the signal into the ADC for the proper value and the A6 Digital

 

assembly’s gate array for interrupts or overloads. The 2nd pass test sets the 1st pass result to

 

zero and checks the signal into the ADC for the proper value and the A6 Digital assembly’s

 

gate array for interrupts or overloads. The zero test checks for minimal output while the gate

 

array outputs zero data.

[ BASEBAND ]

This test verifies that the A6 Digital assembly’s gate arrays are operating correctly. The trigger

 

gate array provides dc input data. The signal is then measured at 0 Hz for 63.58 Vpk ±0.635V

 

and from 4 Hz to 1.6 kHz for 0 Vpk ±0.06358V.

[ DGTL SRCE THRU

This test verifies that the A6 Digital assembly’s gate arrays and digital source are operating

DSP ]

correctly. In this test, the digital source outputs a periodic chirp to the gate arrays. The

 

resultant spectrum is then checked from 384 Hz to 51.2 kHz.

[ DIGITAL FILTER ]

This test verifies that the digital filter’s gate array on the A6 Digital assembly is operating

 

correctly. The A7 CPU assembly’s microprocessor configures the digital filter’s gate array

 

over the fast bus. The microprocessor then reads the control lines to check circuits internal to

 

the gate array and verify correct configuration. This test also writes to and reads from the gate

 

array’s RAM, checking for stuck bits. The Trigger Gate Array test [ TRIGGER ] and the LO

 

Gate Array test [ LO ] must pass for this test to pass. No data paths on the A6 Digital assembly

 

are checked.

[ DISK CONTROLLR ] This test verifies that the disk controller on the A7 CPU assembly is operating correctly. In this test, the microprocessor sends a series of writes to and reads from the disk controller.

[ DISK FIFO ]

This test verifies that the disk controller’s FIFO on the A7 CPU assembly is operating

 

correctly. In this test, the CPU assembly’s microprocessor writes 2048 pseudo-random bytes to

 

the disk FIFO. The microprocessor then reads the disk FIFO.

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Agilent Technologies 35670-90066 manual Individual Self-Test Descriptions, Dgtl Srce Thru