| Agilent 35670A | Internal Test Descriptions |
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[ SERIAL PORT ] | This test verifies that the | |
| receiving data. In this test, the user connects the transmit data line to the recieve data line. | |
| Data is sent out on the transmit data line and read back on the receive data line. | |
[ SEEK RECORD ] | This test verifies that the A100 Disk Drive assembly’s head can move to a user specified record | |
| on the flexible disk. In this test, the disk controller on the A7 CPU assembly instructs the | |
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| in the range of valid record numbers. The default record number is 0. This test requires a | |
| formatted flexible disk. |
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[ SOURCE LO ] | This test verifies that the local oscillator (LO) gate array on the A6 Digital assembly is | |
| operating correctly. In this test, the A7 CPU assembly’s microprocessor configures the LO | |
| gate array and reads its control lines to check circuits internal to the gate array and verify | |
| correct configuration. No data paths on the Digital assembly are checked. | |
[ SOURCE TO CPU ] | This test verifies that the core of the digital source on the A6 Digital assembly is operating | |
| correctly. In this test, the A7 CPU assembly’s microprocessor configures the digital source to | |
| output a 12.8 kHz chirp. The microprocessor then reads the final chirp value in the | |
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[ TACHOMETR ] | This test verifies that the tachometer circuits on the A10 Rear Panel assembly and A6 Digital | |
| assembly are operating correctly. In this test, a BNC cable must be connected from the source | |
| connector to the tachometer connector. The tachometer pulses are counted for 200 | |
| milliseconds with the source turned off. The count should be zero. Next the source is set to | |
| 100 Hz, 3.53 Vrms and the tachometer pulses are counted for another 200 milliseconds. This | |
| time the count should be 20 ±1. |
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[ TRIGGER ] | This test verifies that the trigger gate array on the A6 Digital assembly | is operating correctly. |
| In this test, the A7 CPU assembly’s microprocessor configures the trigger gate array. The | |
| microprocessor then reads the control lines to check circuits internal to the gate array and verify | |
| correct configuration. This test also verifies functions internal to the gate array such as internal | |
| trigger level, trigger interrupts, overload interrupts, and post trigger delay. | |
[ WITH LO ] | This test verifies the capability of the A5 Analog assembly’s analog source to output a flat | |
| zoomed periodic chirp signal. In this test, the A6 Digital assembly’s local oscillator is used | |
| with the analog source to produce a zoomed periodic chirp signal. The signal is connected to | |
| the input channels via the calibration path (CALP). The flatness of the signal is measured from | |
| 13.6 kHz to 26.4 kHz. |
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[ WITHOUT LO ] | This test verifies the capability of the A5 Analog assembly’s analog source to output a flat | |
| baseband chirp signal. In this test, the Analog assembly’s analog source outputs a baseband | |
| chirp signal (starting at 0 Hz) that is connected to the A1 Input assembly or A2 Input | |
| assemblies via the calibration path (CALP). The flatness of the signal is measured from | |
| 384 Hz to 51.2 kHz. |
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[ ZOOM ] | This test checks most of the DSP chain, including the LO gate array. In this test, the Digital | |
| assembly’s trigger gate array outputs a dc value to the DSP chain. |
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