Agilent Technologies 35670-90066 manual Pins A7 P2 A102

Agilent 35670A	Voltages and Signals
	A102 DC-DC Converter

A102 DC-DC Converter

The following table lists signals routed between the A7 CPU assembly and the

A102 DC-DC Converter assembly. This table shows several things — if the assembly generates or uses the signal or voltage, and if a signal is bidirectional. A description of each signal follows the table.

Signal Name	Pin(s)	A7 P2	A102
HSYNCELn	11	S	•
VCLK	13	S	•
VID	15	S	•
VSYNCEL	9	S	•
+12 V	1, 2	•	•
+5 V	3, 4	•	•
Gnd	7, 8, 10, 12, 14, 16	•	•
Not Used	5, 6	—	—

SThis assembly is the source of the signal.

• This assembly uses the signal.

— This assembly does not use this signal.

HSYNCELn	Horizontal Synchronization — A low on this line causes a horizontal retrace on the
	A101 Display assembly. Between each HSYNCELn pulse, 560 pixels are sent to the Display
	assembly.
VCLK	Video Clock — This 20 MHz clock provides the timing reference for HSYNCELn, VID, and
	VSYNCEL. The rising edge of this clock determines setup and hold times.
VID	Video Data — This is the serial data line for the A101 Display assembly. This line transmits
	video data to the Display assembly. The video data is transmitted at the VCLK rate between
	horizontal and vertical retraces (during the time HSYNCELn is high and VSYNCEL is low).
	Only the first 400 lines of data are displayed after a VSYNCEL pulse.
VSYNCEL	Vertical Synchronization — A high on this line causes a vertical retrace on the A101 Display
	assembly.

9-37