68030 CPU Package: 128-pin PGA

Accessories Required: HP 10316G

Maximum Clock Speed: 25 MHz input

Signal Line Loading: 100 KΩ plus 18 pF on all lines except DSACK0 and

DSACK1.

Microprocessor Cycles Identified: User data read/write

User program read

Supervisor program read

Bus grant

CPU space accesses including:

Breakpoint acknowledge

Access level control

Coprocessor communication

Interrupt acknowledge

Additional Capabilities: The logic analyzer captures all bus cycles, including prefetches. The 68030 microprocessor must be operating with the internal cache memory and MMU disabled for the logic analyzer to provide inverse assembly.

Maximum Power Required: None

Number of Probes Used: Five 16-channel probes

Microprocessor Specific Measurements

HP 16510B

14 - 16

Front-panel Reference

Page 240
Image 240
HP 16500A, 16510B manual DSACK1