HP 16510B, 16500A Specifications and Characteristics, Introduction Specifications, State Mode

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Specifications and Characteristics

Introduction

Specifications

This appendix lists the specifications, operating characteristics, and supplemental characteristics of the HP 16510B Logic Analyzer Module.

Probes Minimum Swing: 600 mV peak-to-peak.

Threshold Accuracy:
Voltage Range		Accuracy
	−2.0V to +2.0V	150 mV
	−9.9V to −2.1V	300 mV
	+2.1V to +9.9V	300 mV

State Mode

Clock Repetition Rate: Single phase is 35 MHz maximum. With time or state counting, minimum time between states is 60 ns. Both mixed and demultiplexed clocking use master-slave clock timing; master clock must follow slave clock by at least 10 ns and precede the next slave clock by > 50 ns.

Clock Pulse Width: ≥10 ns at threshold.

Setup Time: Data must be present prior to clock transition, ≥10 ns.

Hold Time: Data must be present after rising clock transition on all pods; 0 ns. Data must be present after falling clock transition on pods 1,3 and 5; 0 ns. Data must be present after falling clock transition on pods 2 and 4; 1 ns.

HP 16510B	Specifications and Operating Characteristics
Front-Panel Reference	C-1