Ol Overall Effort Level, Olstdmedhigh

Chapter 7: MAP

•If you do not specify an output file name with the –o option, the output file has the same name as the input file, with a .ncd extension. The file is placed in the input file’s directory

•If you specify an output file name with instead of /home/designs/cpu_dec.ncd) directory.

no path specifier (for example, cpu_dec.ncd , the NCD file is placed in the current working

•If you specify an output file name with a full path specifier (for example, /home/designs/cpu_dec.ncd), the output file is placed in the specified directory.

If the output file already exists, it is overwritten with the new NCD file. You do not receive a warning when the file is overwritten.

Note: However, signals connected to pads or to the outputs of BUFTs, flip-flops, latches, and

RAMS are preserved for back-annotation.

–ol (Overall Effort Level)

–ol[stdmedhigh]

The –ol option is available when running timing-driven packing and placement with the – timing option. The –ol option sets the overall MAP effort level. The effort level specifies the level of effort MAP uses to pack the design.

Of the three effort_level values, use std for low effort level (fastest runtime at expense of QOR), use med for medium effort level (balance of runtime and QOR), use high for high effort level (best QOR with increased runtime).

The default effort level in MAP is high. Following is command line syntax for using the

–ol option, set to std:

map –timing –ol std design.ncd output.ncd design.pcf

Note: The –ol option is ignored if the –timing option is not set.

–p (Part Number)

–ppart

Specifies the Xilinx part number for the device. The syntax for the –p option is described in “–p (Part Number)” in Chapter 1.

If you do not specify a part number using the –p option, MAP selects the part specified in the input NGD file. If the information in the input NGD file does not specify a complete device and package, you must enter a device and package specification using the –p option. MAP supplies a default speed value, if necessary.

The architecture you specify with the –p option must match the architecture specified within the input NGD file. You may have chosen this architecture when you ran NGDBuild or during an earlier step in the design entry process (for example, you may have specified the architecture as an attribute within a schematic, or specified it as an option to a netlist reader). If the architecture does not match, you have to run NGDBuild again and specify the desired architecture.

You can only enter a part number or device name from a device library you have installed on your system. For example, if you have not installed the 4006E device library, you cannot create a design using the 4006E–PC84 part.

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Development System Reference Guide

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i manual Ol Overall Effort Level, Olstdmedhigh

Models: 8.2i