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Xilinx 8.2i manual 4Logical Circuit Representation

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Chapter 7: MAP

This command creates a back-annotated simulation netlist using the logical-to-physical cross-reference file named mapped.ngm. This cross-reference file contains information about the logical design netlist, and the back-annotated simulation netlist (mapped.nga) is actually a back-annotated version of the logical design. However, if MAP makes a physical error, for example, implements an Active Low function for an Active High function, this error will not be detected in the mapped.nga file and will not appear in the simulation netlist.

For example, consider the following logical circuit generated by NGDBuild from a design file, shown in the following figure.

A * B + C * D

D Q

CLK

X8549

Figure 7-4:Logical Circuit Representation

Observe the Boolean output from the combinatorial logic. Suppose that after running MAP for the preceding circuit, you obtain the following result.

CLB

LUT

A * B + C * D

D Q

CLK

X8550

Figure 7-5:CLB Configuration

Observe that MAP has generated an active low (C) instead of an active high (C). Consequently, the Boolean output for the combinatorial logic is incorrect. When you run NetGen using the mapped.ngm file, you cannot detect the logical error because the delays are back-annotated to the correct logical design, and not to the physical design.

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Development System Reference Guide

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Xilinx 8.2i manual 4Logical Circuit Representation

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Contents

Development System Reference Guide Development System Reference Guide Guide Contents About This GuidePreface About This Guide Typographical Additional ResourcesConventions Allow block blockname Online DocumentPreface About This Guide Convention Meaning or Use Example Loc1 loc2 ... locnTable of Contents Tcl PARTGen MAP Logical Design Rule CheckNGDBuild Physical Design Rule Check PARDevelopment System Reference Guide XPower PIN2UCFTrace Trace Output FilesSpeedprint BitGenBSDLAnno PROMGen IBISWriterTAEngine CPLDfitTsim Hprep6 NetGenDevelopment System Reference Guide Xflow Data2MEM EDIF2NGD, and NGDBuildIntroduction Command Line Program Overview1Command Line Programs in the Design Flow Design Flow Step Execute Commands File Command Line SyntaxCommand Line Options IntroductionHelp Command Line OptionsSymbol Description Programname -harchitecturename Introduction Symbol DescriptionIntstyle Integration Style Programname -h filename2Part Number Examples Specification Part NumberInvoking Command Line Programs Introduction 2Part Number Examples SpecificationDesign Flow Design Flow OverviewDesign Flow Xilinx Design FlowDesign Flow Overview 2Xilinx Software Design Flow FPGAs3Xilinx Software Design Flow CPLDs Design Entry and Synthesis Design Entry and SynthesisHierarchical Design Core Generator Tool FPGAs Only Schematic Entry OverviewLibrary Elements Constraints HDL Entry and SynthesisFunctional Simulation Mapping Constraints FPGAs OnlyDesign Implementation Block PlacementTiming Specifications Netlist Translation ProgramsDesign Implementation 5Design Implementation Flow FPGAs6Design Implementation Flow CPLDs Bitstream Generation FPGAs Only Mapping FPGAs OnlyPlacing and Routing FPGAs Only Design Verification 1Verification Tools Verification TypeDesign Verification 7Three Verification Methods of the Design Flow FPGAsSimulation Back-Annotation9Back-Annotation Flow for FPGAs Schematic-Based Simulation NetGenHDL-Based Simulation Timing Simulation11Simulation Points for HDL Designs 2Five Simulation Points in HDL Design Flow UniSim SimPrimStatic Timing Analysis FPGAs Only Xilinx Design Download Cables In-Circuit VerificationDesign Rule Checker FPGAs Only ProbeDesign Size and Performance 3Global Clock Resources Fpga Family Number Destination PinsFpga Design Tips Global Clock DistributionData Feedback and Clock Enable 12 Gated Clock13Synchronous Design Using Data Feedback CountersQ0. . . .Q7Q8. . . .Q15 Other Synchronous Design ConsiderationsQ0. . . .Q7 Q8. . . .Q15 Tcl Tcl OverviewAccessing Help Xilinx Tcl ShellTcl Fundamentals Tcl FundamentalsXilinx Namespace Xilinx Tcl Commands1Xilinx Tcl Commands for General Usage Subcommands Project create and manage projects Partition support design preservation Tcl Commands for General Usage2Xilinx Tcl Commands for Advanced Scripting Subcommands Get get partition properties Tcl Commands for General UsageDelete delete a partition Partition delete /stopwatch/Instdcm1Partition new /stopwatch/Instdcm1 New create a new partitionPartition get /stopwatch/Instdcm1 preserve Partition properties Properties list available partition propertiesRerun force partition synthesis and implementation Set set partition preserve property 4Process Tasks Process run and manage project processesRun run process task Project create and manage projects Clean remove system-generated project filesProject clean Getprocesses get project processes Close close the ISE projectGet get project properties Project closeProject getprocesses -instance Instdcm1 New create a new ISE projectOpen open an ISE project Project new watchver.iseProject properties -process all Properties list project propertiesSet set project properties, values, and options Project set Map Effort Level high Set device set deviceSet family set device family Project set device xc2vp2Project set family Virtex2p Set package set device packageSet speed set device speed Project set package fg256Delete delete timing analysis Timinganalysis generate timing analysis reportsSet top set the top-level module/entity Project set speedDisableconstraints disable timing constraints Disablecpt disable components for path tracing controlStopwatchtiming TSclk=PERIOD TIMEGROUP\sclk\ Enablecpt enable components for path tracing controlTiminganalysis enableconstraints Ns High 50.00000%Regsrclk ureg1 ureg2 ureg3 Timinganalysis enablecpt stopwatchtimingGet get analysis property Ascii New new timing analysis Run run analysis Reset reset path filters and constraintsTiminganalysis reset stopwatchtiming Saveas save analysis reportTiminganalysis set stopwatchtiming Set set analysis propertiesSetconstraint set constraint for custom analysis AnalysisspeedPeriod 13 sclk Setendpoints set source and destination endpointsTiminganalysis setconstraint stopwatchtiming Timinganalysis setfilter stopwatchtiming nets Setquery set up net or timegroup reportSetfilter set filter for analysis Exclude uregnet1 uregnet2 uregnet3Add add file to project Showsettings generate settings reportXfile manage project files ExampleXfile add *.vhd /mysource/mysubdir timing.ucf Get get project file propertiesRemove remove file from project Xfile get timestamp stopwatch.vhdAppendto add objects to a collection Tcl Commands for Advanced ScriptingCollection create and manage a collection Xfile remove stopwatch.vhdSet colVar1 search * -type instance Tcl Commands for Advanced ScriptingCopy copy a collection Set colVar2 $colVar1Set colVar2 search /top/T* -type instance Equal compare two collectionsSet colVar2 collection copy $colVar1 Collection equal $colVar1 $colVar2Foreach iterate over elements in a collection Get get collection propertySet item collection index $colVar Index extract a collection objectProperties list available collection properties Object name $itemCollection properties Removefrom remove objects from a collectionSet set the property for all collections Collection set displaytype true Object get object informationSizeof show the number of objects in a collection Collection sizeof $colVarCollection foreach obj $colVar set objProps Get get object propertiesName name of the object Object properties $obj foreach prop $objPropsSet colVar search * -type partition Properties list object propertiesObject name collection index $colVar Object type collection index $colVar Search search and return matching objectsType type of object 6Project Properties Property Name Description Project Properties and OptionsSearch /stopwatch -type instance Option Name Synthesis ToolProject Properties and Options NGDBuild Options Option Name Implementation Tool Option Name Implementation Tool Tcl 10 PAR Options Example Tcl Scripts Example Tcl ScriptsSample Tcl Script for General Usage Tcl Sample Tcl Script for Advanced Scripting 100 PARTGen Syntax PARTGenPARTGen Overview Partgen optionsPARTGen Options PARTGen Input FilesPARTGen Output Files Arch Print Information for Specified ArchitecturePARTGen Options Print a List of Devices, Packages, and Speeds PARTGen Options 2s400e Pname Creates Package file and Partlist FilesNopkgfile No Package File Xcv400 Device V400bg432 PartPartlist File Creates Package and Partlist FilesPartlist File HeaderDevice Attributes Part architecture family partname diename packagefilenameSelect RAM PKG File PKG FileDone Logical Design Rule Check Logical DRC OverviewNet Check Logical DRC ChecksBlock Check Pad CheckLogical DRC Checks Clock Buffer CheckName Check 1Checked Primitive Pins NGD Primitive Pins Checked Primitive Pin CheckNGDBuild NGDBuild OverviewConverting a Netlist to an NGD File 1NGDBuild Design FlowNGDBuild Syntax NGDBuild SyntaxNGDBuild Input Files Ngdbuild options designname ngdfile.ngd120 NGDBuild Intermediate Files Add PADs to Top-Level Port SignalsNGDBuild Output Files NGDBuild OptionsDd Destination Directory Aul Allow Unmatched LOCsBm Specify BMM Files Ignore UCF FileNGDBuild Options InsertkeephierarchyLibraries to Search SynopsysModular assemble -pimpath pimdirectorypath Modular assemble Module AssemblyModular initial Initial Budgeting of Modular Design Usepimmodulename1 -usepimmodulename2Modular module -active modulename Modular module Active Module ImplementationNt Netlist Translation Type Pimcreate pimdirectory -ncd designnamerouted.ncdAllow Unexpanded Blocks Ignore LOC ConstraintsSd Search Specified Directory Verbose Report All Messages Uc User Constraints FileUr Read User Rules File Uc ucffile.ucf128 MAP MAP OverviewMAP Syntax Map options infile.ngd pcffile.pcfMAP Input Files MAP Input FilesMAP Output Files MAP Options 1Map Options and ArchitecturesMAP Options 1Map Options and Architectures Bp Map Slice LogicPack CLBs CpackfactorEquivalentregisterremoval Remove Redundant Registers Cm Cover ModeDetail Write Out Detailed MAP Report Cm area speed balancedGf Guide NCD File Gm Guide ModeGm incremental Guide Mode incremental Globalopt Global OptimizationIse ISE Project File Ignorekeephierarchy Ignore Keephierarchy PropertiesIr Do Not Use RLOCs to Generate RPMs Map to Input FunctionsNo logic replication Output File NameOl Overall Effort Level OlstdmedhighRegisterduplication Duplicate Registers Pr Pack Registers in I/ONo Register Ordering Retiming Register Retiming During Global OptimizationTx on off aggressive limit Timing Timing-Driven Packing and PlacementTx Transform Buses Xe Extra Effort Level MAP ProcessDo Not Remove Unused Logic MAP ProcessRegister Ordering Register Ordering Data01 Addr02 Atod03 Dtoa04Guided Mapping 3Guided MappingSimulating Map Results Simulating Map Results4Logical Circuit Representation MAP Report MRP File MAP Report MRP File148 Development System Reference Guide 149 Type Block GND Xstgnd IOB 152 Halting MAP Halting MAP154 Physical Design Rule Check DRC OverviewDRC Output File DRC SyntaxDRC Input File DRC OptionsDRC Checks DRC ChecksReport Incomplete Programming DRC Errors and Warnings PAR Place and Route OverviewPAR Flow Routing PAR ProcessPlacing Timing-driven PARPar -k previous.ncd reentrant.ncd pref.pcf Command Line ExamplesPar input.ncd output.ncd Guided PAR Guided PARPCI Cores PAR Output Files PAR SyntaxPAR Input Files PAR SyntaxPAR Options 1Effort Level Options Function Range DefaultGeneral Options Function Range Default Ol value for the routerExistingfile PAR Options 2General Options Function Range DefaultGuide Options Function Range Default Gf Guide NCD File Execute Commands FileDetailed Listing of Options Re-Entrant Routing Gm Guide ModeIntstyle Integration Style PAR OptionsNopad No Pad Multi-Tasking ModeNumber of PAR Iterations Ol Overall Effort LevelPl Placer Effort Level No PlacementPower Power Aware PAR No RoutingUb Use Bonded I/Os Number of Results to SaveStarting Placer Cost Table Overwrite Existing FilesXe Extra Effort Level Performance Evaluation ModePAR Reports PAR ReportsPlace and Route Report File Development System Reference Guide 175 Ing score in parenthesis Development System Reference Guide 177 Par -n 3 -pl high -rl std address.ncd output.dir Multi Pass Place and Route MpprPlacer effort levelrouter effort levelcost table number Guide Reporting Select I/O Utilization and Usage SummaryImporting the PAD File Information Multi Pass Place and Route MpprBest Performance Mode XplorerXplorer Timing Closure ModeXplorer Syntax Xplorer Options Xplorer Input FilesXplorer Output Files 5Xplorer Options FunctionXplorer Report Xplorer 5Xplorer Options Function184 ReportGen Input Files ReportGenReportGen Syntax ReportGen Output FilesIsexflowsilent ReportGen OptionsOption Usage Function Padfmt padcsvtxtTurns Engine PAR Multi-Tasking Option Turns Engine PAR Multi-Tasking OptionTurns Engine Overview Par -m nodefilename -ol high -n 10 mydesign.ncd output.dirTurns Engine Syntax Turns Engine Input FilesSystem Requirements Turns Engine Output FilesLimitations Turns Engine Environment Variables Debugging Rsh machinenameScreen Output Node Status JOB Time Halting PAR Halting PAR 196 XPower XPower OverviewFpga Designs XPower SyntaxFiles Used by XPower Cpld DesignsVCD Data Entry Using XPowerUsing XPower Limit Rename Power ReportOther Methods of Data Entry Ls List Supported DevicesTb Turn On Time Based Reporting Specify Settings XML Input FileSpecify VCD file Wx Write XML FileStandard Reports Command Line ExamplesPower Reports Advanced Reports Power ReportsDetailed Reports 204 PIN2UCF PIN2UCF OverviewPIN2UCF Flow PIN2UCF Output Files PIN2UCF SyntaxPIN2UCF Input Files PIN2UCF SyntaxWrite to a Report File PIN2UCF OptionsPIN2UCF Scenarios Outfile.ucfExisting Pinlock section. 210 Trace Trace OverviewTrce options design.ncd constraint.pcf Trace SyntaxTrace Input Files Trce -runmacro.xtm design.ncd constraint.pcfTrace Output Files Trace Output FilesInput files to Trace Advanced Analysis Generate an Error ReportTrace Options Fastpaths Report Fastest PathsOutput Timing Report File Name Nodatasheet No Data SheetLimit Timing Report Trace OptionsSkew Analyze Clock Skew for All Clocks Run Run Timing Analyzer MacroChange Speed SkewStampstampfile design.ncd Stamp Generates Stamp timing model filesReport Uncovered Paths UlimitXml XML Output File Name Trace Command Line ExamplesGenerate a Verbose Report VlimitTrace Reports Trace ReportsTiming Verification with Trace Net Delay ConstraintsPath Delay Constraints Net Skew ConstraintsClock Skew and Setup Checking 1Path Delay Constraint Terminology Definition2Clock Skew and Setup Checking Terminology Terms Definition 2Clock Skew Example3Clock Passing Through Multiple Buffers Reporting with Trace 5Error reporting for failed timing constraints Data Sheet Report Development System Reference Guide 227 BSLOT0 D0S Guaranteed Setup and Hold Reporting Report LegendSetup Times Hold TimesSummary Report Without a Physical Constraints File Specified Trce -o summary.twr ramb16s1.ncdTrce -o summary1.twr ramb16s1.ncd clkperiod.pcf Development System Reference Guide 233 Trce -e 3 ramb16s1.ncd clkperiod.pcf -o errorreport.twr Development System Reference Guide 235 236 Development System Reference Guide 237 BUFGMUX.I0 Offset Constraints Offset ConstraintsOffset in Path Details Offset in Constraint ExamplesOffset in Header Offset in Detailed Path Data Offset In with Phase Shifted Clock Offset in Detail Path Clock PathDevelopment System Reference Guide 243 Offset OUT Constraint Examples Offset OUT HeaderOffset OUT Path Details Offset OUT Detail Clock PathOffset OUT Detail Path Data Period Header Period ConstraintsPeriod Constraints Examples Period ConstraintsPeriod Path Period Path Details Period Constraint with Phase Period Path with Phase Halting Trace Minimum Period StatisticsSpeedprint Speedprint OverviewSpeedprint Options Specify TemperatureSpeedprint Syntax Min Display Minimum Speed DataCommand Description Speedprint Example CommandsSpeedprint Example Commands Speedprint Example ReportsLvttl Fast BitGen BitGen OverviewLoutfilename.ll Moutfilename.msk Boutfilename.rbt BitGen SyntaxOption Output File BitGen Input Files BitGen Input FilesBitGen Output Files BitGen Options Create Rawbits FileBitgen -goptionsetting design.ncd design.bit design.pcf Bd Update Block RamsSet Configuration Do Not Run DRCBinary ActiveReconfigActivateGCLK CclkPinConfigRate CompressDebugBitstream DCIUpdateModeDCMShutdown DonePin DisableBandgapDONEcycle DonePipeGclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 DriveDoneEncrypt GSRcycleHswapenPin GWEcycleGTScycle Key0, Key1, Key2, Key3, Key4, Key5LCKcycle KeyFileKeyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5 M0PinMatchcycle M1PinM2Pin PartialGCLKPartialRight PartialMask0, PartialMask1, PartialMask2PartialLeft PersistReadBack PowerdownPinProgPin SecurityStartKey SEURepairStartCBC StartupClkTdoPin TckPinTdiPin TmsPinUserID No BIT FileUnusedPin Create a Partial Bit File Create a Logic Allocation FileGenerate a Mask File Overwrite Existing Output File276 BSDLAnno BSDLAnno OverviewBSDLAnno Output Files BSDLAnno SyntaxBSDLAnno Input Files BSDLAnno OptionsGeneric Parameter BSDLAnno File CompositionEntity Declaration BSDLAnno File CompositionLogical Port Description Package Pin-MappingTAP Description USE StatementScan Port Identification Bsdl File Modifications for Single-Ended Pins Boundary Register DescriptionExplanation Header Comments Boundary Scan Behavior in Xilinx DevicesModifications to the Designwarning Section BSDLAnno BSDLAnno version numberPROMGen PROMGen OverviewPROMGen Output Files PROMGen SyntaxPROMGen Input Files Promgen optionsPROMGen Options Load Prom File Add BIT FIlesProm Format File1.bit file2.bitLoad Upward Prom SizeTemplate File Ver VersionEnable Compression Bit Swapping in Prom FilesPROMGen Examples PROMGen Examples292 IBISWriter IBISWriter OverviewIBISWriter Syntax Ibiswriter options infile outfile.ibsIBISWriter Options IBISWriter Input FilesIBISWriter Output Files Set Reference VoltageMl Multilingual Support Architecture Option Value DescriptionPin Generate Package Parasitics IBISWriter Options298 CPLDfit CPLDfit OverviewCPLDfit Output Files CPLDfit SyntaxCPLDfit Input Files CPLDfit Options Keepio Prevent Optimization of Unused Inputs Inputs Number of Inputs to Use During OptimizationIostd Specify I/O Standard Loc Keep Specified Location ConstraintsNogsropt Disable Global Set/Reset Optimization Nofbnand Disable Use of Foldback NandsNogclkopt Disable Global Clock Optimization Nogtsopt Disable Global Output-Enable OptimizationSpecify Xilinx Part Power Set Power ModeOptimize Optimize Logic for Density or Speed Pinfbk Use Pin FeedbackSlew Set Slew Rate Terminate Set to Termination ModeUnused Set Termination Mode of Unused I/Os Wysiwyg Do Not Perform Optimization306 Tsim Tsim SyntaxTsim Input Files TAEngine TAEngine OverviewTAEngine Syntax 1TAEngine Design FlowIopath Trace Paths TAEngine OptionsDetail Detail Report Specify Output Filename312 Hprep6 1Hprep6 Design FlowAutosig Automatically Generate Signature Hprep6 SyntaxHprep6 Options Produce ISC File Nopullup Disable PullupsSpecify Signature Value for Readback Tmv Specify Test Vector File316 NetGen NetGen OverviewNetGen 1NetGen Output File Types Input Design FileNetGen Supported Flows NetGen Simulation FlowNetGen Functional Simulation Flow NetGen Simulation FlowOutput files for NetGen Functional Simulation NetGen Timing Simulation FlowSyntax for NetGen Functional Simulation Ngcbuildoptions toplevelnetlistfile outputngcfileNetGen Timing Simulation Flow Syntax for NetGen Timing SimulationFpga Timing Simulation Input files for Cpld Timing Simulation Output files for Fpga Timing SimulationCpld Timing Simulation Output files for Cpld Timing SimulationOptions for NetGen Simulation Flow Module Simulation of Active Module Insertppbuffers Insert Path Pulse BuffersMhf Multiple Hierarchical Files Change Speed Ofmt Output FormatPcf PCF File Sim Generate Simulation NetlistTp Bring Out Global 3-State Net as Port Ti Top Instance NameTm Top Module Name Insertglbl Insert glbl.v ModuleSdfanno Include $sdfannotate Ne No Name EscapingPf Generate PIN File Sdfpath Full Path to SDF FileVHDL-Specific Options for Functional and Timing Simulation NetGen Equivalence Checking Flow NetGen Equivalence Checking FlowXon Select Output Behavior for Timing Violations Xon truefalseSyntax for NetGen Equivalence Checking Input files for NetGen Equivalence CheckingEcn Equivalence Checking Output files for NetGen Equivalence CheckingOptions for NetGen Equivalence Checking Flow Module Verification of Active Module NetGen Static Timing Analysis Flow NetGen Static Timing Analysis FlowNgm Design Correlation File Syntax for NetGen Static Timing Analysis Input files for Static Timing AnalysisOutput files for Static Timing Analysis Options for NetGen Static Timing Analysis Flow 336 Preserving and Writing Hierarchy Files Preserving and Writing Hierarchy FilesSta Generate Static Timing Analysis Netlist Modulename .sim Modulename .ecn Modulename .staHierarchy Information File Dedicated Global Signals in Back-Annotation SimulationTestbench File Dedicated Global Signals in Back-Annotation Simulation Global Signals in Verilog NetlistGlobal Signals in Vhdl Netlist 340 Xflow Xflow OverviewXflow Syntax 1XFLOW Design FlowXflow Input Files Xflow Input FilesXflow Output Files Xflow Output Files 1XFLOW Output Files FPGAs and CPLDs2XFLOW Output Files FPGAs Xflow Flow Types Assemble Module AssemblyXflow Flow Types 3XFLOW Output Files CPLDsEcn Create a File for Equivalence Checking Config Create a BIT File for FPGAsConfigoptionfile 4Option Files for -assemble Flow Type Description5Option Files for -ecn Flow Type Description Fit Fit a CpldFsim Create a File for Functional Simulation 6Option Files for -fit Flow Type DescriptionXflow -p xc2v250fg256-5 -fsim genericverilog.opt testclk.v Implement Implement an Fpga7Option Files for -fsim Flow Type Implement optionfileInitial budget.opt Initial Initial Budgeting of Modular DesignXflow Flow Types 8Option Files for -implement Flow Type Xflow -p xc2v250fg256-5 -initial budget.opt top.edf9Option Files for -module Flow Type Module Active Module ImplementationModuleoptionfile -activemodulename 10Option Files for -mppr Flow Type Description Mppr Multi-Pass Place and Route for FPGAsSta Create a File for Static Timing Analysis 11Option Files for -sta Flow Type DescriptionSynthoptionfile SynthSynthesis Types 12Option Files for -synth Flow Type Description Tsim Create a File for Timing SimulationOption Files for -synth Flow Types Testclk.prjFlow Files 13Option Files for -tsim Flow Type DescriptionFlow File Format FpgaExports Flag Enabled DisabledTriggers ReportsUser Command Blocks End Program programnameXflow Option Files Option File FormatEd Copy Files to Export Directory Xflow OptionsActive Active Module Specify a Global VariableOoutputfilename Norun Creates a Script File OnlyChange Output File Name Xflow -implement balanced.opt -o newname testclk.edfPdpimdirectory Pd PIMs DirectoryRd Copy Report Files RdreportdirectoryWd Specify a Working Directory Using Xflow Flow Types in CombinationRunning Xflow Running Smart FlowRunning Xflow Using the SCR, BAT, or TCL FileUsing the Xilxflowpath Environment Variable 366 Data2MEM Data2MEM OverviewBlock RAM Memory Map .bmm files Data2MEM SyntaxData2MEM Input and Output Files Executable and Linkable Format .elf filesBit .bit files Debugging Information Format Dwarf .drf filesMemory .mem files Verilog .v filesVhdl .vhd files 1Data2MEM Command Line Options DescriptionData2MEM Options UCF .ucf filesData2MEM Options 1Data2MEM Command Line Options Pp filename Xilinx Development System Files Name Type Produced By DescriptionAppendix MOD Ascii Trace NKY TCL Ascii 378 EDIF2NGD, and NGDBuild EDIF2NGDEDIF2NGD Design Flow EDIF2NGD Output Files EDIF2NGD SyntaxEDIF2NGD Input Files Edif2ngd options ediffile ngofileAul Allow Unmatched LOCs Add PADs to Top-Level Port SignalsEDIF2NGD Options Ignore LOC Constraints Libraries to SearchPart Number LlibnameNGDBuild NGDBuild and the Netlist ReadersNGDBuild Bus Naming Conventions Netlist Launcher NetlisterBus Matching Busnameindex DI3Netlist Launcher Netlister User Rules and System Rules Netlist Launcher Rules FilesUser Rules File User Rules FormatDevelopment System Reference Guide 389 System Rules File Value Types in Key StatementsRules File Examples Example 1 Edfrule System RuleExample 2 User Rule Example 3 User RuleNGDBuild File Names and Locations NGDBuild File Names and LocationsExample 4 User Rule 394 Glossary AbelAsic Bonded BitstreamBlock Boundary scanBuft CAECLB CmosCombinatorial logic ConfigurationContention CompilerDangling bus CpldDaisy chain Dangling netDRC DSPEDA EdifFifo EpromFdsd Fmap FpgaGlobal buffers Global Set/Reset netGate array Global 3-state netHDL IbufIeee IFDJedec LSB MSB NCD NGMPAL PIM PLDProm RAMRTL ROMRPM Signal SDF standard delay formatSet/reset Startup symbolTCL Trace TsimTTL Vital WireVhdl Xtclsh422