Xilinx 8.2i manual Project create and manage projects, Clean remove system-generated project files

Chapter 3: Tcl

Table 3-4:Process Tasks

“Translate”

“Map”

“Generate Post-Map Static Timing”

“Generate Post-Map Simulation Model”

“Place & Route”

“Generate Primetime Netlist”

“Generate Post-Place & Route Static Timing”

“Generate Post-Place & Route Simulation Model”

“Generate IBIS Model”

“Back-Annotate Pin Locations”

“Generate Programming File”

R

project (create and manage projects)

The project command creates and manages ISE projects. A project contains all files and data related to a design. You can create a project to manage all of the design files and to enable different processes to work on the design.

%project <subcommand>

clean (remove system-generated project files)

The project clean command removes all of the temporary and system-generated files in the current ISE project. It does not remove any source files, like Verilog or VHDL, nor does it remove any user-modified files. For example, system generated design and report files like the NCD (.ncd) and map report (.mpr) are removed with the project clean command, unless they have been user-modified.

% project clean

project is the name of the Xilinx Tcl command.

clean is the name of the project subcommand.

Example:	% project clean
Description:	In this example, the current ISE project is cleaned. All temporary
	and system generated files are removed, including design and
	report files, unless these have been user-modified.

Tcl Return:

True if the project is cleaned successfully; false otherwise.

Caution! The project clean command permanently deletes all system-generated files from the current ISE project. These files include the NGD and NCD files generated by the implementation tools.

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