Xilinx 8.2i manual Pr Pack Registers in I/O, No Register Ordering, Start Placer Cost Table

Models: 8.2i

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MAP Options

–pr (Pack Registers in I/O)

–pr {i o b}

By default (without the –pr option), MAP only places flip-flops or latches within an I/O cell if your design entry method specifies that these components are to be placed within I/O cells. For example, if you create a schematic using IFDX (Input D Flip-Flop) or OFDX (Output D Flip-Flop) design elements, the physical components corresponding to these design elements must be placed in I/O cells. The –pr option specifies that flip-flops or latches may be packed into input registers (i selection), output registers (o selection), or both (b selection) even if the components have not been specified in this way.

–r (No Register Ordering)

By default (without the –r option), MAP looks at the register bit names for similarities and tries to map register bits in an ordered manner (called register ordering). If you specify the -r option, register bit names are ignored when registers are mapped, and the bits are not mapped in any special order. For a description of register ordering, see “Register Ordering”.

–register_duplication (Duplicate Registers)

The –register_duplication option is only available when running timing-driven packing and placement with the –timing option. The –register_duplication option duplicates registers to improve timing when running timing-driven packing. See “–timing (Timing- Driven Packing and Placement).”

–retiming (Register Retiming During Global Optimization)

–retiming onoff

When this option is on, registers are moved forward or backwards through the logic to balance out the delays in a timing path to increase the overall clock frequency. The overall number of registers may be altered due to the processing. This option is available for Virtex-4 designs. By default, this option is off.

Note: This option is available only when “–global_opt (Global Optimization)” is used.

–t (Start Placer Cost Table)

–tplacer_cost_table

The –t option is only available when running timing-driven packing and placement with the –timing option. The –t option specifies the cost table at which the placer starts (placer cost tables are described in Chapter 9, “PAR”). The placer_cost_table range is 1–100. The default is 1.

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Xilinx 8.2i manual Pr Pack Registers in I/O, No Register Ordering, Registerduplication Duplicate Registers