R

Tcl Commands for General Usage

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

new_file_name specifies the file name for the analysis report.

Example:

% timing_analysis saveas stopwatch_timing stopwatch_report

 

 

Description:

In this example, the timing_analysis saveas command is used to save

 

the stopwatch_timing analysis to a report file named

 

stopwatch_report.

Tcl Return:

Name of the report file.

set (set analysis properties)

The timing_analysis set command is used to set properties and values for an analysis.

%timing_analysis set <analysis_name> <property> <value>

timing_analysis is the name of the Xilinx Tcl command.

set is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

property specifies the analysis property that you wish to set the value for. See Table 3-5for a list of analysis properties.

value specifies the value for the specified property.

Example:

% timing_analysis set stopwatch_timing

 

analysis_speed -11

 

 

Description:

In this example, the timing_analysis set command is used to set the

 

value of the analysis_speed property to -11, for the stopwatch_timing

 

analysis.

Tcl Return:

Previous value of the specified property.

set_constraint (set constraint for custom analysis)

The timing_analysis set_constraint command is used to set constraints for a custom analysis.

%timing_analysis set_constraint <analysis_name> <constraint_type> <constraint_details>

timing_analysis is the name of the Xilinx Tcl command.

set_constraint is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

constraint_type specifies the type of constraint to set for the custom analysis. There are four constraint types:

♦maxdelay—pad-to-pad maximum delay

♦period—period constraint on clock pad

Development System Reference Guide

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Xilinx 8.2i manual Set set analysis properties, Setconstraint set constraint for custom analysis, Analysisspeed
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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.
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