Xilinx 8.2i manual Flow File Format, Fpga

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XFLOW Flow Types

The following table lists the flow files invoked for each flow type.

Table 23-14:Xilinx Flow Files

Flow Type	Flow File	Devices	Flow Phase	Programs Run
–synth	fpga.flw	FPGA	Synthesis	XST, Synplicity,
				Leonardo Spectrum
–initial			Modular Design Initial Budgeting Phase	NGDBuild
–module			Modular Design Active Module	NGDBuild, MAP, PAR
			Implementation Phase
–assemble			Modular Design Final Assembly Phase	NGDBuild, MAP, PAR
–implement			Implementation	NGDBuild, MAP, PAR,
				TRACE
–mppr			Implementation (with Multi-Pass Place	NGDBuild, MAP, PAR
			and Route)	(multiple passes), TRACE
–tsim			Timing	NGDBuild, NetGen
			Simulation
–ecn			Equivalence Checking	NGDBuild, NetGen
–sta			Static Timing Analysis	NGDBuild, NetGen
–config			Configuration	BitGen
–synth	cpld.flw	CPLD	Synthesis	XST, Synplicity,
				Leonardo Spectrum
–fit			Fit	NGDBuild, CPLDfit,
				TAEngine, HPREP6
–tsim			Timing	TSim, NetGen
			Simulation
–synth	fsim.flw	FPGA/	Synthesis	XST, Synplicity,
		CPLD		Leonardo Spectrum
–fsim			Functional	NGDBuild, NetGen
			Simulation

Flow File Format

The flow file is an ASCII file that contains the following information:

Note: You can use variables for the file names listed on the Input, Triggers, Export, and Report

lines. For example, if you specify Input: <design>.vhd on the Input line, XFLOW automatically reads the VHDL file in your working directory as the input file.

•ExportDir

This section specifies the directory in which to copy the output files of the programs in the flow. The default directory is your working directory.

Note: You can also specify the export directory using the –ed command line option. The command line option overrides the ExportDir specified in the flow file.

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