Boundary Register Description

Chapter 15: BSDLAnno

The boundary register description gives the structure of the boundary scan cells on the device. Each pin on a device may have up to three boundary scan cells, with each cell consisting of a register and a latch. Boundary scan test vectors are loaded into or scanned from these registers.

For example (from the xcv50e_pq240.bsd file): attribute BOUNDARY_REGISTER of XCV50E_PQ240 : entity is

--cellnum (type, port, function, safe[, ccell, disval, disrslt]) " 0 (BC_1, *, controlr, 1)," &

" 1 (BC_1, IO_P184, output3, X, 0, 1, PULL0)," & -- PAD48 " 2 (BC_1, IO_P184, input, X)," & -- PAD48

Every IOB has three boundary scan registers associated with it: control, output, and input. BSDLAnno modifies the boundary register description as described in the “BSDL File Modifications for Single-Ended Pins” and “BSDL File Modifications for Differential Pins” sections.

BSDL File Modifications for Single-Ended Pins

If pin 57 has been configured as a single-ended tri-state output pin, no code modifications are required:

--TRISTATE OUTPUT PIN (three state output with an input component) " 9 (BC_1, *, controlr, 1)," &

" 10 (BC_1, PAD57, output3, X, 9, 1, Z)," & " 11 (BC_1, PAD57, input, X)," &

If pin 57 is configured as a single-ended input, modify as follows:

--PIN CONFIGURED AS AN INPUT " 9 (BC_1, *, internal, 1)," & " 10 (BC_1, *, internal, X)," & " 11 (BC_1, PAD57, input, X)," &

If pin 57 is configured as a single-ended output, it is treated as a single-ended bidirectional pin:

--PIN CONFIGURED AS AN OUTPUT " 9 (BC_1, *, controlr, 1)," &

" 10 (BC_1, PAD57, output3, X, 9, 1, Z)," & " 11 (BC_1, PAD57, input, X)," &

If pin 57 is unconfigured or not used in the design, do not modify:

--PIN CONFIGURED AS "UNUSED"

"9 (BC_1, *, controlr, 1)," &

"10 (BC_1, PAD57, output3, X, 9, 1, PULL0)," &

"11 (BC_1, PAD57, input, X)," &

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Development System Reference Guide

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i manual Boundary Register Description, Bsdl File Modifications for Single-Ended Pins

Models: 8.2i

Chapter 15: BSDLAnno