Xilinx 8.2i manual Ing score in parenthesis

Chapter 9: PAR

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Phase 12.5

Phase 12.5 (Checksum:7270df4) REAL time: 47 secs

Writing design to file c:\test\par0.ncd

Total REAL time to Placer completion: 47 secs

Total CPU time to Placer completion: 8 secs

The router portion of the PAR report shows that the router has been invoked. It displays each phase of the router and reports the number of unrouted nets, in addition to an approximate tim-

ing score in parenthesis.
Starting	Router
Phase 1:	231 unrouted;		REAL time: 51		secs
Phase 2:	154 unrouted;		REAL time: 51		secs
Phase 3:	21	unrouted;	REAL time: 51	secs
Phase 4:	21	unrouted; (347)	REAL time: 51				secs
Phase 5:	21	unrouted; (0)	REAL time:	51		secs
Phase 6:	21	unrouted; (0)	REAL time:	51		secs

Phase 7: 0 unrouted; (0)		REAL time:	51 secs
Total	REAL time to Router completion: 51		secs
Total	CPU time to Router	completion: 10 secs

Generating "par" statistics.

The next portion of the PAR report contains the Clock Report, which includes a clock table that

lists all clocks in the design and provides information on the routing resources, number of

fanout, maximum net skew for each clock, and maximum delay. The Locked column in the clock

table means the clock driver (BUFGMUX) is assigned to a particular site instead of left floating.

Note: The clock skew and delay listed in this table differ from the skew and delay reported in

TRACE, or Timing Analyzer. PAR takes into account the net that drives the clock pins whereas

TRACE and Timing Analyzer include the entire clock path.

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