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Xilinx 8.2i manual Drc, Dsp

Models: 8.2i

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decimal

Decimal refers to a numbering system with a base of 10 digits starting with zero.

decoder

A decoder is a symbol that translates n input lines of binary information into 2n output lines. It is the opposite of an encoder.

Delay Locked Loop (DLL)

A digital circuit used to perform clock management functions on and off-chip.

density

Density is the number of gates on a device.

design implementation

Design implementation is a design implementation specification as opposed to the functional specification of the design. The implementation specification refers to the actual implementation of the design from low-level components expressed in bits. The functional specification refers to the definition of the design or circuit function.

device

A device is an integrated circuit or other solid-state circuit formed in semiconducting materials during manufacturing.

digital

Digital refers to the representation of information by code of discrete elements, as opposed to the continuous scale of analog representation.

DONE pin

The DONE pin is a dual-function pin. As an input, it can be configured to delay the global logic initialization or the enabling of outputs. As an output, it indicates the completion of the configuration process.

downloading

Downloading is the process of configuring or programming a device by sending bitstream data to the device.

DRC

The Design Rule Checker (DRC). A program that checks the (NCD) file for design implementations for errors.

DSP

Digital Signal Processing (DSP). A powerful and flexible technique of processing analog (linear) signals in digital form used in CoreGen.

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Development System Reference Guide

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Xilinx 8.2i manual Drc, Dsp

Contents

Development System Reference Guide Development System Reference Guide Guide Contents About This GuidePreface About This Guide Additional Resources ConventionsTypographical Allow block blockname Online DocumentPreface About This Guide Convention Meaning or Use Example Loc1 loc2 ... locnTable of Contents Tcl PARTGen Logical Design Rule Check NGDBuildMAP Physical Design Rule Check PARDevelopment System Reference Guide XPower PIN2UCFTrace Trace Output FilesSpeedprint BitGenBSDLAnno PROMGen IBISWriterCPLDfit TsimTAEngine Hprep6 NetGenDevelopment System Reference Guide Xflow Data2MEM EDIF2NGD, and NGDBuildCommand Line Program Overview 1Command Line Programs in the Design Flow Design Flow StepIntroduction Execute Commands File Command Line SyntaxCommand Line Options IntroductionCommand Line Options Symbol DescriptionHelp Programname -harchitecturename Introduction Symbol DescriptionIntstyle Integration Style Programname -h filename2Part Number Examples Specification Part NumberInvoking Command Line Programs Introduction 2Part Number Examples SpecificationDesign Flow Design Flow OverviewDesign Flow Xilinx Design FlowDesign Flow Overview 2Xilinx Software Design Flow FPGAs3Xilinx Software Design Flow CPLDs Design Entry and Synthesis Hierarchical DesignDesign Entry and Synthesis Schematic Entry Overview Library ElementsCore Generator Tool FPGAs Only Constraints HDL Entry and SynthesisFunctional Simulation Mapping Constraints FPGAs OnlyDesign Implementation Block PlacementTiming Specifications Netlist Translation ProgramsDesign Implementation 5Design Implementation Flow FPGAs6Design Implementation Flow CPLDs Mapping FPGAs Only Placing and Routing FPGAs OnlyBitstream Generation FPGAs Only Design Verification 1Verification Tools Verification TypeDesign Verification 7Three Verification Methods of the Design Flow FPGAsSimulation Back-Annotation9Back-Annotation Flow for FPGAs Schematic-Based Simulation NetGenHDL-Based Simulation Timing Simulation11Simulation Points for HDL Designs 2Five Simulation Points in HDL Design Flow UniSim SimPrimStatic Timing Analysis FPGAs Only Xilinx Design Download Cables In-Circuit VerificationDesign Rule Checker FPGAs Only ProbeDesign Size and Performance 3Global Clock Resources Fpga Family Number Destination PinsFpga Design Tips Global Clock DistributionData Feedback and Clock Enable 12 Gated Clock13Synchronous Design Using Data Feedback CountersOther Synchronous Design Considerations Q0. . . .Q7 Q8. . . .Q15Q0. . . .Q7Q8. . . .Q15 Tcl Tcl OverviewAccessing Help Xilinx Tcl ShellTcl Fundamentals Tcl FundamentalsXilinx Tcl Commands 1Xilinx Tcl Commands for General Usage SubcommandsXilinx Namespace Project create and manage projects Tcl Commands for General Usage 2Xilinx Tcl Commands for Advanced Scripting SubcommandsPartition support design preservation Get get partition properties Tcl Commands for General UsageDelete delete a partition Partition delete /stopwatch/Instdcm1New create a new partition Partition get /stopwatch/Instdcm1 preservePartition new /stopwatch/Instdcm1 Properties list available partition properties Rerun force partition synthesis and implementationPartition properties Set set partition preserve property Process run and manage project processes Run run process task4Process Tasks Clean remove system-generated project files Project cleanProject create and manage projects Getprocesses get project processes Close close the ISE projectGet get project properties Project closeProject getprocesses -instance Instdcm1 New create a new ISE projectOpen open an ISE project Project new watchver.iseProperties list project properties Set set project properties, values, and optionsProject properties -process all Project set Map Effort Level high Set device set deviceSet family set device family Project set device xc2vp2Project set family Virtex2p Set package set device packageSet speed set device speed Project set package fg256Delete delete timing analysis Timinganalysis generate timing analysis reportsSet top set the top-level module/entity Project set speedDisableconstraints disable timing constraints Disablecpt disable components for path tracing controlStopwatchtiming TSclk=PERIOD TIMEGROUP\sclk\ Enablecpt enable components for path tracing controlTiminganalysis enableconstraints Ns High 50.00000%Timinganalysis enablecpt stopwatchtiming Get get analysis propertyRegsrclk ureg1 ureg2 ureg3 Ascii New new timing analysis Run run analysis Reset reset path filters and constraintsTiminganalysis reset stopwatchtiming Saveas save analysis reportTiminganalysis set stopwatchtiming Set set analysis propertiesSetconstraint set constraint for custom analysis AnalysisspeedSetendpoints set source and destination endpoints Timinganalysis setconstraint stopwatchtimingPeriod 13 sclk Timinganalysis setfilter stopwatchtiming nets Setquery set up net or timegroup reportSetfilter set filter for analysis Exclude uregnet1 uregnet2 uregnet3Add add file to project Showsettings generate settings reportXfile manage project files ExampleXfile add *.vhd /mysource/mysubdir timing.ucf Get get project file propertiesRemove remove file from project Xfile get timestamp stopwatch.vhdAppendto add objects to a collection Tcl Commands for Advanced ScriptingCollection create and manage a collection Xfile remove stopwatch.vhdSet colVar1 search * -type instance Tcl Commands for Advanced ScriptingCopy copy a collection Set colVar2 $colVar1Set colVar2 search /top/T* -type instance Equal compare two collectionsSet colVar2 collection copy $colVar1 Collection equal $colVar1 $colVar2Foreach iterate over elements in a collection Get get collection propertySet item collection index $colVar Index extract a collection objectProperties list available collection properties Object name $itemRemovefrom remove objects from a collection Set set the property for all collectionsCollection properties Collection set displaytype true Object get object informationSizeof show the number of objects in a collection Collection sizeof $colVarCollection foreach obj $colVar set objProps Get get object propertiesName name of the object Object properties $obj foreach prop $objPropsProperties list object properties Object name collection index $colVarSet colVar search * -type partition Search search and return matching objects Type type of objectObject type collection index $colVar 6Project Properties Property Name Description Project Properties and OptionsSearch /stopwatch -type instance Option Name Synthesis ToolProject Properties and Options NGDBuild Options Option Name Implementation Tool Option Name Implementation Tool Tcl 10 PAR Options Example Tcl Scripts Sample Tcl Script for General UsageExample Tcl Scripts Tcl Sample Tcl Script for Advanced Scripting 100 PARTGen Syntax PARTGenPARTGen Overview Partgen optionsPARTGen Options PARTGen Input FilesPARTGen Output Files Arch Print Information for Specified ArchitecturePARTGen Options Print a List of Devices, Packages, and Speeds PARTGen Options 2s400e Pname Creates Package file and Partlist FilesNopkgfile No Package File Xcv400 Device V400bg432 PartPartlist File Creates Package and Partlist FilesPartlist File HeaderDevice Attributes Part architecture family partname diename packagefilenameSelect RAM PKG File PKG FileDone Logical Design Rule Check Logical DRC OverviewNet Check Logical DRC ChecksBlock Check Pad CheckClock Buffer Check Name CheckLogical DRC Checks 1Checked Primitive Pins NGD Primitive Pins Checked Primitive Pin CheckNGDBuild NGDBuild OverviewConverting a Netlist to an NGD File 1NGDBuild Design FlowNGDBuild Syntax NGDBuild SyntaxNGDBuild Input Files Ngdbuild options designname ngdfile.ngd120 NGDBuild Intermediate Files Add PADs to Top-Level Port SignalsNGDBuild Output Files NGDBuild OptionsDd Destination Directory Aul Allow Unmatched LOCsBm Specify BMM Files Ignore UCF FileNGDBuild Options InsertkeephierarchyLibraries to Search SynopsysModular assemble -pimpath pimdirectorypath Modular assemble Module AssemblyModular initial Initial Budgeting of Modular Design Usepimmodulename1 -usepimmodulename2Modular module -active modulename Modular module Active Module ImplementationNt Netlist Translation Type Pimcreate pimdirectory -ncd designnamerouted.ncdIgnore LOC Constraints Sd Search Specified DirectoryAllow Unexpanded Blocks Verbose Report All Messages Uc User Constraints FileUr Read User Rules File Uc ucffile.ucf128 MAP MAP OverviewMAP Syntax Map options infile.ngd pcffile.pcfMAP Input Files MAP Output FilesMAP Input Files MAP Options 1Map Options and ArchitecturesMAP Options 1Map Options and Architectures Bp Map Slice LogicPack CLBs CpackfactorEquivalentregisterremoval Remove Redundant Registers Cm Cover ModeDetail Write Out Detailed MAP Report Cm area speed balancedGf Guide NCD File Gm Guide ModeGm incremental Guide Mode incremental Globalopt Global OptimizationIse ISE Project File Ignorekeephierarchy Ignore Keephierarchy PropertiesIr Do Not Use RLOCs to Generate RPMs Map to Input FunctionsNo logic replication Output File NameOl Overall Effort Level OlstdmedhighRegisterduplication Duplicate Registers Pr Pack Registers in I/ONo Register Ordering Retiming Register Retiming During Global OptimizationTiming Timing-Driven Packing and Placement Tx Transform BusesTx on off aggressive limit Xe Extra Effort Level MAP ProcessDo Not Remove Unused Logic MAP ProcessRegister Ordering Register Ordering Data01 Addr02 Atod03 Dtoa04Guided Mapping 3Guided MappingSimulating Map Results Simulating Map Results4Logical Circuit Representation MAP Report MRP File MAP Report MRP File148 Development System Reference Guide 149 Type Block GND Xstgnd IOB 152 Halting MAP Halting MAP154 Physical Design Rule Check DRC OverviewDRC Output File DRC SyntaxDRC Input File DRC OptionsDRC Checks Report Incomplete ProgrammingDRC Checks DRC Errors and Warnings PAR Place and Route OverviewPAR Flow Routing PAR ProcessPlacing Timing-driven PARCommand Line Examples Par input.ncd output.ncdPar -k previous.ncd reentrant.ncd pref.pcf Guided PAR Guided PARPCI Cores PAR Output Files PAR SyntaxPAR Input Files PAR SyntaxPAR Options 1Effort Level Options Function Range DefaultGeneral Options Function Range Default Ol value for the routerPAR Options 2General Options Function Range Default Guide Options Function Range DefaultExistingfile Execute Commands File Detailed Listing of OptionsGf Guide NCD File Re-Entrant Routing Gm Guide ModeIntstyle Integration Style PAR OptionsNopad No Pad Multi-Tasking ModeNumber of PAR Iterations Ol Overall Effort LevelPl Placer Effort Level No PlacementPower Power Aware PAR No RoutingUb Use Bonded I/Os Number of Results to SaveStarting Placer Cost Table Overwrite Existing FilesXe Extra Effort Level Performance Evaluation ModePAR Reports PAR ReportsPlace and Route Report File Development System Reference Guide 175 Ing score in parenthesis Development System Reference Guide 177 Multi Pass Place and Route Mppr Placer effort levelrouter effort levelcost table numberPar -n 3 -pl high -rl std address.ncd output.dir Guide Reporting Select I/O Utilization and Usage SummaryImporting the PAD File Information Multi Pass Place and Route MpprBest Performance Mode XplorerTiming Closure Mode Xplorer SyntaxXplorer Xplorer Options Xplorer Input FilesXplorer Output Files 5Xplorer Options FunctionXplorer Report Xplorer 5Xplorer Options Function184 ReportGen Input Files ReportGenReportGen Syntax ReportGen Output FilesIsexflowsilent ReportGen OptionsOption Usage Function Padfmt padcsvtxtTurns Engine PAR Multi-Tasking Option Turns Engine PAR Multi-Tasking OptionTurns Engine Overview Par -m nodefilename -ol high -n 10 mydesign.ncd output.dirTurns Engine Syntax Turns Engine Input FilesTurns Engine Output Files LimitationsSystem Requirements Turns Engine Environment Variables Debugging Rsh machinenameScreen Output Node Status JOB Time Halting PAR Halting PAR 196 XPower XPower OverviewFpga Designs XPower SyntaxFiles Used by XPower Cpld DesignsUsing XPower Using XPowerVCD Data Entry Limit Rename Power ReportOther Methods of Data Entry Ls List Supported DevicesTb Turn On Time Based Reporting Specify Settings XML Input FileSpecify VCD file Wx Write XML FileCommand Line Examples Power ReportsStandard Reports Power Reports Detailed ReportsAdvanced Reports 204 PIN2UCF PIN2UCF OverviewPIN2UCF Flow PIN2UCF Output Files PIN2UCF SyntaxPIN2UCF Input Files PIN2UCF SyntaxWrite to a Report File PIN2UCF OptionsPIN2UCF Scenarios Outfile.ucfExisting Pinlock section. 210 Trace Trace OverviewTrce options design.ncd constraint.pcf Trace SyntaxTrace Input Files Trce -runmacro.xtm design.ncd constraint.pcfTrace Output Files Input files to TraceTrace Output Files Advanced Analysis Generate an Error ReportTrace Options Fastpaths Report Fastest PathsOutput Timing Report File Name Nodatasheet No Data SheetLimit Timing Report Trace OptionsSkew Analyze Clock Skew for All Clocks Run Run Timing Analyzer MacroChange Speed SkewStampstampfile design.ncd Stamp Generates Stamp timing model filesReport Uncovered Paths UlimitXml XML Output File Name Trace Command Line ExamplesGenerate a Verbose Report VlimitTrace Reports Trace ReportsTiming Verification with Trace Net Delay ConstraintsPath Delay Constraints Net Skew ConstraintsClock Skew and Setup Checking 1Path Delay Constraint Terminology Definition2Clock Skew and Setup Checking Terminology Terms Definition 2Clock Skew Example3Clock Passing Through Multiple Buffers Reporting with Trace 5Error reporting for failed timing constraints Data Sheet Report Development System Reference Guide 227 BSLOT0 D0S Guaranteed Setup and Hold Reporting Report LegendSetup Times Hold TimesSummary Report Without a Physical Constraints File Specified Trce -o summary.twr ramb16s1.ncdTrce -o summary1.twr ramb16s1.ncd clkperiod.pcf Development System Reference Guide 233 Trce -e 3 ramb16s1.ncd clkperiod.pcf -o errorreport.twr Development System Reference Guide 235 236 Development System Reference Guide 237 BUFGMUX.I0 Offset Constraints Offset ConstraintsOffset in Constraint Examples Offset in HeaderOffset in Path Details Offset in Detailed Path Data Offset In with Phase Shifted Clock Offset in Detail Path Clock PathDevelopment System Reference Guide 243 Offset OUT Constraint Examples Offset OUT HeaderOffset OUT Path Details Offset OUT Detail Clock PathOffset OUT Detail Path Data Period Header Period ConstraintsPeriod Constraints Examples Period ConstraintsPeriod Path Period Path Details Period Constraint with Phase Period Path with Phase Halting Trace Minimum Period StatisticsSpeedprint Speedprint OverviewSpeedprint Options Specify TemperatureSpeedprint Syntax Min Display Minimum Speed DataCommand Description Speedprint Example CommandsSpeedprint Example Commands Speedprint Example ReportsLvttl Fast BitGen BitGen OverviewBitGen Syntax Option Output FileLoutfilename.ll Moutfilename.msk Boutfilename.rbt BitGen Input Files BitGen Output FilesBitGen Input Files BitGen Options Create Rawbits FileBitgen -goptionsetting design.ncd design.bit design.pcf Bd Update Block RamsSet Configuration Do Not Run DRCBinary ActiveReconfigActivateGCLK CclkPinConfigRate CompressDCIUpdateMode DCMShutdownDebugBitstream DonePin DisableBandgapDONEcycle DonePipeGclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 DriveDoneEncrypt GSRcycleHswapenPin GWEcycleGTScycle Key0, Key1, Key2, Key3, Key4, Key5LCKcycle KeyFileKeyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5 M0PinMatchcycle M1PinM2Pin PartialGCLKPartialRight PartialMask0, PartialMask1, PartialMask2PartialLeft PersistReadBack PowerdownPinProgPin SecurityStartKey SEURepairStartCBC StartupClkTdoPin TckPinTdiPin TmsPinNo BIT File UnusedPinUserID Create a Partial Bit File Create a Logic Allocation FileGenerate a Mask File Overwrite Existing Output File276 BSDLAnno BSDLAnno OverviewBSDLAnno Output Files BSDLAnno SyntaxBSDLAnno Input Files BSDLAnno OptionsGeneric Parameter BSDLAnno File CompositionEntity Declaration BSDLAnno File CompositionLogical Port Description Package Pin-MappingUSE Statement Scan Port IdentificationTAP Description Bsdl File Modifications for Single-Ended Pins Boundary Register DescriptionExplanation Header Comments Boundary Scan Behavior in Xilinx DevicesModifications to the Designwarning Section BSDLAnno BSDLAnno version numberPROMGen PROMGen OverviewPROMGen Output Files PROMGen SyntaxPROMGen Input Files Promgen optionsPROMGen Options Load Prom File Add BIT FIlesProm Format File1.bit file2.bitLoad Upward Prom SizeTemplate File Ver VersionEnable Compression Bit Swapping in Prom FilesPROMGen Examples PROMGen Examples292 IBISWriter IBISWriter OverviewIBISWriter Syntax Ibiswriter options infile outfile.ibsIBISWriter Options IBISWriter Input FilesIBISWriter Output Files Set Reference VoltageMl Multilingual Support Architecture Option Value DescriptionPin Generate Package Parasitics IBISWriter Options298 CPLDfit CPLDfit OverviewCPLDfit Syntax CPLDfit Input FilesCPLDfit Output Files CPLDfit Options Keepio Prevent Optimization of Unused Inputs Inputs Number of Inputs to Use During OptimizationIostd Specify I/O Standard Loc Keep Specified Location ConstraintsNogsropt Disable Global Set/Reset Optimization Nofbnand Disable Use of Foldback NandsNogclkopt Disable Global Clock Optimization Nogtsopt Disable Global Output-Enable OptimizationSpecify Xilinx Part Power Set Power ModeOptimize Optimize Logic for Density or Speed Pinfbk Use Pin FeedbackSlew Set Slew Rate Terminate Set to Termination ModeUnused Set Termination Mode of Unused I/Os Wysiwyg Do Not Perform Optimization306 Tsim Tsim SyntaxTsim Input Files TAEngine TAEngine OverviewTAEngine Syntax 1TAEngine Design FlowIopath Trace Paths TAEngine OptionsDetail Detail Report Specify Output Filename312 Hprep6 1Hprep6 Design FlowHprep6 Syntax Hprep6 OptionsAutosig Automatically Generate Signature Produce ISC File Nopullup Disable PullupsSpecify Signature Value for Readback Tmv Specify Test Vector File316 NetGen NetGen OverviewNetGen 1NetGen Output File Types Input Design FileNetGen Supported Flows NetGen Simulation FlowNetGen Functional Simulation Flow NetGen Simulation FlowOutput files for NetGen Functional Simulation NetGen Timing Simulation FlowSyntax for NetGen Functional Simulation Ngcbuildoptions toplevelnetlistfile outputngcfileSyntax for NetGen Timing Simulation Fpga Timing SimulationNetGen Timing Simulation Flow Input files for Cpld Timing Simulation Output files for Fpga Timing SimulationCpld Timing Simulation Output files for Cpld Timing SimulationOptions for NetGen Simulation Flow Insertppbuffers Insert Path Pulse Buffers Mhf Multiple Hierarchical FilesModule Simulation of Active Module Change Speed Ofmt Output FormatPcf PCF File Sim Generate Simulation NetlistTp Bring Out Global 3-State Net as Port Ti Top Instance NameTm Top Module Name Insertglbl Insert glbl.v ModuleSdfanno Include $sdfannotate Ne No Name EscapingPf Generate PIN File Sdfpath Full Path to SDF FileVHDL-Specific Options for Functional and Timing Simulation NetGen Equivalence Checking Flow NetGen Equivalence Checking FlowXon Select Output Behavior for Timing Violations Xon truefalseSyntax for NetGen Equivalence Checking Input files for NetGen Equivalence CheckingOutput files for NetGen Equivalence Checking Options for NetGen Equivalence Checking FlowEcn Equivalence Checking Fn Control Flattening a Netlist Module Verification of Active ModuleNetGen Static Timing Analysis Flow Ngm Design Correlation FileNetGen Static Timing Analysis Flow Input files for Static Timing Analysis Output files for Static Timing AnalysisSyntax for NetGen Static Timing Analysis Options for NetGen Static Timing Analysis Flow Aka Write Also-Known-As Names as Comments336 Preserving and Writing Hierarchy Files Preserving and Writing Hierarchy FilesSta Generate Static Timing Analysis Netlist Modulename .sim Modulename .ecn Modulename .staDedicated Global Signals in Back-Annotation Simulation Testbench FileHierarchy Information File Global Signals in Verilog Netlist Global Signals in Vhdl NetlistDedicated Global Signals in Back-Annotation Simulation 340 Xflow Xflow OverviewXflow Syntax 1XFLOW Design FlowXflow Input Files Xflow Input FilesXflow Output Files Xflow Output Files 1XFLOW Output Files FPGAs and CPLDs2XFLOW Output Files FPGAs Xflow Flow Types Assemble Module AssemblyXflow Flow Types 3XFLOW Output Files CPLDsEcn Create a File for Equivalence Checking Config Create a BIT File for FPGAsConfigoptionfile 4Option Files for -assemble Flow Type Description5Option Files for -ecn Flow Type Description Fit Fit a CpldFsim Create a File for Functional Simulation 6Option Files for -fit Flow Type DescriptionXflow -p xc2v250fg256-5 -fsim genericverilog.opt testclk.v Implement Implement an Fpga7Option Files for -fsim Flow Type Implement optionfileInitial budget.opt Initial Initial Budgeting of Modular DesignXflow Flow Types 8Option Files for -implement Flow Type Xflow -p xc2v250fg256-5 -initial budget.opt top.edfModule Active Module Implementation Moduleoptionfile -activemodulename9Option Files for -module Flow Type 10Option Files for -mppr Flow Type Description Mppr Multi-Pass Place and Route for FPGAsSta Create a File for Static Timing Analysis 11Option Files for -sta Flow Type DescriptionSynth Synthesis TypesSynthoptionfile 12Option Files for -synth Flow Type Description Tsim Create a File for Timing SimulationOption Files for -synth Flow Types Testclk.prjFlow Files 13Option Files for -tsim Flow Type DescriptionFlow File Format FpgaExports Flag Enabled DisabledTriggers ReportsUser Command Blocks End Program programnameXflow Option Files Option File FormatEd Copy Files to Export Directory Xflow OptionsActive Active Module Specify a Global VariableOoutputfilename Norun Creates a Script File OnlyChange Output File Name Xflow -implement balanced.opt -o newname testclk.edfPdpimdirectory Pd PIMs DirectoryRd Copy Report Files RdreportdirectoryWd Specify a Working Directory Using Xflow Flow Types in CombinationRunning Xflow Running Smart FlowUsing the SCR, BAT, or TCL File Using the Xilxflowpath Environment VariableRunning Xflow 366 Data2MEM Data2MEM OverviewBlock RAM Memory Map .bmm files Data2MEM SyntaxData2MEM Input and Output Files Executable and Linkable Format .elf filesBit .bit files Debugging Information Format Dwarf .drf filesMemory .mem files Verilog .v filesVhdl .vhd files 1Data2MEM Command Line Options DescriptionData2MEM Options UCF .ucf filesData2MEM Options 1Data2MEM Command Line Options Partname Pp filenameXilinx Development System Files Name Type Produced By DescriptionAppendix MOD Ascii Trace NKY TCL Ascii 378 EDIF2NGD, and NGDBuild EDIF2NGDEDIF2NGD Design Flow EDIF2NGD Output Files EDIF2NGD SyntaxEDIF2NGD Input Files Edif2ngd options ediffile ngofileAdd PADs to Top-Level Port Signals EDIF2NGD OptionsAul Allow Unmatched LOCs Ignore LOC Constraints Libraries to SearchPart Number LlibnameNGDBuild NGDBuild and the Netlist ReadersNGDBuild Bus Naming Conventions Netlist Launcher NetlisterBus Matching Busnameindex DI3Netlist Launcher Netlister User Rules and System Rules Netlist Launcher Rules FilesUser Rules File User Rules FormatDevelopment System Reference Guide 389 System Rules File Value Types in Key StatementsRules File Examples Example 1 Edfrule System RuleExample 2 User Rule Example 3 User RuleNGDBuild File Names and Locations Example 4 User RuleNGDBuild File Names and Locations 394 Glossary AbelAsic Bonded BitstreamBlock Boundary scanBuft CAECLB CmosCombinatorial logic ConfigurationContention CompilerDangling bus CpldDaisy chain Dangling netDRC DSPEDA EdifEprom FdsdFifo Fmap FpgaGlobal buffers Global Set/Reset netGate array Global 3-state netHDL IbufIeee IFDJedec LSB MSB NCD NGMPAL PIM PLDProm RAMROM RPMRTL Signal SDF standard delay formatSet/reset Startup symbolTCL Trace TsimTTL Vital WireVhdl Xtclsh422