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XFLOW Flow Types

The following table lists the output files that can be generated for CPLDs.

Table 23-3:XFLOW Output Files (CPLDs)

File Name

Description

To Generate this File...

 

 

 

design_name.gyd

This ASCII file is a CPLD guide file.

Flow file must include “cpldfit”

 

 

(Use the –fit flow type)

 

 

 

design_name.jed

This ASCII file contains configuration data

Flow file must include “hprep6”

 

that can be downloaded to a CPLD using

(Use the –fit flow type)

 

iMPACT.

 

 

 

 

 

design_name.rpt

This report file contains information about

Flow file must include “cpldfit”

 

the CPLDfit run, in which a logical design is

(Use the –fit flow type)

 

fit to a CPLD.

 

 

 

 

 

design_name.tim

This report file contains timing data.

Flow file must include “taengine” (

 

 

Use the –fit flow type)

 

 

 

XFLOW Flow Types

A “flow” is a sequence of programs invoked to synthesize, implement, simulate, and configure a design. For example, to implement an FPGA design the design is run through the NGDBuild, MAP, and PAR programs.

“Flow types” instruct XFLOW to execute a particular flow as specified in the relative flow file. (For more information on flow files, see, “Flow Files”.) You can enter multiple flow types on the command line to achieve a desired flow. This section describes the flow types you can use.

Note: All flow types require that an option file be specified. If you do not specify an option file,

XFLOW issues an error.

–assemble (Module Assembly)

–assembleoption_file –pdpim_directory_path

Note: This flow type supports FPGA device families only.

This flow type runs the final phase of the Modular Design flow. In this “Final Assembly” phase, the team leader assembles the top-level design and modules into one NGD file and then implements the file.

Note: Use of this option assumes that you have completed the Initial Budgeting and Active Implementation phases of Modular Design. See “–implement (Implement an FPGA)” and “–initial (Initial Budgeting of Modular Design)” for details.

This flow type invokes the fpga.flw flow file and runs NGDBuild to create the NGD file that contains logic from the top-level design and each of the Physically Implemented Modules (PIMs). XFLOW then implements the NGD file by running MAP and PAR to create a fully expanded NCD file.

The working directory for this flow type should be the top-level design directory. You can either run the –assemble flow type from the top-level directory or use the –wd option to specify this directory. Specify the path to the PIMs directory after the –pd option. If you do not use the –pd option, XFLOW searches the working directory for the PIM files.The input design file should be the NGO file for the top-level design.

Development System Reference Guide

www.xilinx.com

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Xilinx 8.2i manual Xflow Flow Types, Assemble Module Assembly, 3XFLOW Output Files CPLDs
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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.
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