Syntax for NetGen Timing Simulation

NetGen Timing Simulation Flow

Input file types depend on whether you are using an FPGA or CPLD design. Please refer to “FPGA Timing Simulation” and “CPLD Timing Simulation” for design-specific information, including input file types.

A complete list of command line options for performing NetGen Timing Simulation appears at the end of this section.

The following command runs the NetGen Timing Simulation flow:

netgen -sim-ofmt{verilogvhdl} [options] input_file[.ncd]

verilog or vhdl is the output netlist format that you specify with the required –ofmt option.

options is one or more of the options listed in the “Options for NetGen Simulation Flow” section. In addition to common options, this section also contains Verilog and VHDL- specific options.

input_file is the input NCD file name and extension.

To get help on command line usage for NetGen Timing Simulation, type:

netgen -h sim

FPGA Timing Simulation

You can verify the timing of an FPGA design using the NetGen Timing Simulation flow to generate a Verilog or VHDL netlist and an SDF file. The figure below illustrates the NetGen Timing Simulation flow using an FPGA design.

NCD

PCF

ELF

NetGen

V/VHD SDF Simprim

Library

Simulation Tool

X10250

Figure 22-2:FPGA Timing Simulation

The FPGA Timing Simulation flow uses the following files as input:

•NCD —This physical design file may be mapped only, partially or fully placed, or partially or fully routed.

•PCF (optional)—This is a physical constraints file. If prorated voltage or temperature is applied to the design, the PCF must be included to pass this information to NetGen. See “–pcf (PCF File)” for more information.

•ELF (MEM) (optional)—This file populates the Block RAMs specified in the .bmm file. See “–bd (Block RAM Data File)” for more information.

Development System Reference Guide

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8.2i specifications

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Xilinx 8.2i manual Syntax for NetGen Timing Simulation, Fpga Timing Simulation

Models: 8.2i

NetGen Timing Simulation Flow