Syntax for NetGen Equivalence Checking

Chapter 22: NetGen

ELF NCD NGM

NetGen

SVF/VXC V Formal

Library

Formal Verification Tool

X10034

Figure 22-5:Post-Implementation Flow for FPGAs

Syntax for NetGen Equivalence Checking.

The following command runs the NetGen Equivalence Checking flow:

netgen -ecn[tool_name] [options] input_file[.ncd/.ngd] [ngm_file.ngm]

options is one or more of the options listed in the “Options for NetGen Equivalence Checking Flow” section.

tool_name is a required switch that generates a netlist compatible with equivalence checking tools. Valid tool_name arguments are conformal or formality. For additional information on equivalence checking and formal verification tools, please refer to the Synthesis and Simulation Design Guide.

input_file is the input NCD or NGD file. If an NGD file is used, the .ngd extension must be specified.

ngm_file (optional, but recommended) is the input NGM file, which is a design file, produced by MAP, that contains information about what was trimmed and transformed during the MAP process.

To get help on command line usage for NetGen Timing Simulation, type:

netgen -h ecn

Input files for NetGen Equivalence Checking

The NetGen Equivalence Checking flow uses the following files as input:

•NGD file—This file is a logical description of an unmapped FPGA design.

•NCD file—This physical design file may be mapped only, partially or fully placed, or partially or fully routed.

•NGM file —This mapped design file is generated by MAP and contains information on what was trimmed and transformed during the MAP process. See “–ngm (Design Correlation File)” for more information.

•ELF (MEM) (optional)—This file is used to populate the Block RAMs specified in the

.bmm file. See “–bd (Block RAM Data File)” for more information.

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Development System Reference Guide

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i Syntax for NetGen Equivalence Checking, Input files for NetGen Equivalence Checking

Models: 8.2i