Chapter 12: TRACE

R

Clock Path: rclk_in to ffl_reg

 

 

Location

Delay type

Delay(ns)

Logical Resource(s)

-------------------------------------------------

 

-------------------

A8.I

Tiopi

0.825

rclk_in

 

 

 

read_ibufg

CM_X1Y1.CLKIN

net (fanout=1)

0.798

rclk_ibufg

CM_X1Y1.CLK90

Tdcmino

-4.290

read_dcm

UFGMUX5P.I0

net (fanout=1)

0.852

rclk_90_dcm

BUFGMUX5P.O

Tgi0o

0.589

read90_bufg

4.OTCLK1

net (fanout=2)

0.593

rclk_90

------------------------------------------------

 

--------------------

Total -0.633ns (-2.876ns logic, 2.243ns route)

 

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OFFSET OUT Constraint Examples

The following section describe specific examples of an OFFSET OUT constraint, as shown in the Timing Constraints section of a timing report. For clarification, the OFFSET OUT constraint information is divided into the following parts:

OFFSET OUT Header

OFFSET OUT Path Details

OFFSET OUT Detail Clock Path

OFFSET OUT Detail Path Data

OFFSET OUT Header

The header includes the constraint, the number of items analyzed, and number of timing errors detected. See the PERIOD Header for more information on items analyzed and timing errors.

Example:

====================================================================

Timing constraint: OFFSET = OUT 10 nS AFTER COMP "rclk_in" ;

50 items analyzed, 0 timing errors detected.

Minimum allowable offset is 9.835ns.

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Development System Reference Guide

Page 244
Image 244
Xilinx 8.2i manual Offset OUT Constraint Examples, Offset OUT Header

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

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