Chapter 22: NetGen

R

Note: Do not use GR, GSR, PRLD, PRELOAD, or RESET as port names, because these are reserved names in the Xilinx software. This option is ignored by UNISIM-based flows, which use an NGC file as input.

–insert_pp_buffers (Insert Path Pulse Buffers)

–insert_pp_buffers truefalse

The –insert_pp_buffers option controls whether path pulse buffers are inserted into the output netlist to eliminate pulse swallowing. Pulse swallowing is seen on signals in back- annotated timing simulations when the pulse width is shorter than the delay on the input port of the component. For example, if a clock of period 5 ns (2.5 ns high/2.5 ns low) is propagated through a buffer, but in the SDF, the PORT or IOPATH delay for the input port of that buffer is greater than 2.5 ns, the output will be unchanged in the waveform window (e.g., if the output was "X" at the start of simulation, it will remain at "X").

By default this command is set to false.

Note: This option is available when the input is an NCD file.

–intstyle (Integration Style)

–intstyle {ise xflow silent}

The –intstyle option reduces screen output based on the integration style you are running. When using the –intstyle option, one of three modes must be specified: ise, xflow, or silent. The mode sets the way information is displayed in the following ways:

–intstyle ise

This mode indicates the program is being run as part of an integrated design environment.

–intstyle xflow

This mode indicates the program is being run as part of an integrated batch flow.

–intstyle silent

This mode limits screen output to warning and error messages only.

Note: The -intstyle option is automatically invoked when running in an integrated environment, such as Project Navigator or XFLOW.

–mhf (Multiple Hierarchical Files)

The –mhf option is used to write multiple hierarchical files--one for every module that has the KEEP_HIERARCHY attribute.

Note: See “Preserving and Writing Hierarchy Files” for additional information.

–module (Simulation of Active Module)

–module

The –module option creates a netlist file based on the active module only, independent of the top-level design. NetGen constructs the netlist based only on the active module’s interface signals.

To use this option you must specify an NCD file that contains an expanded active module.

Note: The –moduleoption is for use with the Modular Design flow.

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Xilinx 8.2i Insertppbuffers Insert Path Pulse Buffers, Mhf Multiple Hierarchical Files, Module Simulation of Active Module
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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.
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