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Xilinx 8.2i manual 1NetGen Output File Types Input Design File

Models: 8.2i

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Chapter 22: NetGen

The flow type that NetGen runs is based on the input design file (NGC, NGD, or NCD). The following table shows the output file types, based on the input design files:

Table 22-1:NetGen Output File Types

Input Design File	Output File Type

NGC	UNISIM-based functional
	simulation netlist

NGD	SIMPRIM-based functional
	netlist

NCA from CPLD	SIMPRIM-based netlist,
	along with a full timing
	SDF file.

NCD from MAP	SIMPRIM-based netlist,
	along with a partial timing
	SDF file

NCD from PAR	SIMPRIM-based netlist,
	along with a full timing
	SDF file

NetGen can take an implemented design file and write out a single netlist for the entire design, or multiple netlists for each module of a hierarchical design. Individual modules of a design can be simulated on their own, or together at the top-level. Modules identified with the KEEP_HIERARCHY attribute are written as user-specified Verilog, VHDL, and SDF netlists with the “–mhf (Multiple Hierarchical Files)”option. See “Preserving and Writing Hierarchy Files” for additional information.

The following figure outlines the NetGen flow for implemented FPGA designs.

NGD

Logical Design

MAP

NCD

Physical Design

(Mapped)

PAR

NCD

Physical Design

(Placed and Routed)

NCD

NGM

PCF

NetGen

Simulation Netlist

Equivalence Checking

Netlist

Static Timing Analysis

Netlist

X9980

Figure 22-1: NetGen Flow

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Development System Reference Guide

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Xilinx 8.2i manual 1NetGen Output File Types Input Design File

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Contents

Development System Reference Guide Development System Reference Guide Guide Contents About This Guide Preface About This Guide Additional Resources ConventionsTypographical Allow block blockname Online DocumentPreface About This Guide Convention Meaning or Use Example Loc1 loc2 ... locn Table of Contents Tcl PARTGen Logical Design Rule Check NGDBuildMAP Physical Design Rule Check PAR Development System Reference Guide XPower PIN2UCF Trace Trace Output Files Speedprint BitGen BSDLAnno PROMGen IBISWriter CPLDfit TsimTAEngine Hprep6 NetGen Development System Reference Guide Xflow Data2MEM EDIF2NGD, and NGDBuild Command Line Program Overview 1Command Line Programs in the Design Flow Design Flow StepIntroduction Execute Commands File Command Line SyntaxCommand Line Options Introduction Command Line Options Symbol DescriptionHelp Programname -harchitecturename Introduction Symbol DescriptionIntstyle Integration Style Programname -h filename 2Part Number Examples Specification Part Number Invoking Command Line Programs Introduction 2Part Number Examples Specification Design Flow Design Flow Overview Design Flow Xilinx Design Flow Design Flow Overview 2Xilinx Software Design Flow FPGAs 3Xilinx Software Design Flow CPLDs Design Entry and Synthesis Hierarchical DesignDesign Entry and Synthesis Schematic Entry Overview Library ElementsCore Generator Tool FPGAs Only Constraints HDL Entry and SynthesisFunctional Simulation Mapping Constraints FPGAs Only Design Implementation Block PlacementTiming Specifications Netlist Translation Programs Design Implementation 5Design Implementation Flow FPGAs 6Design Implementation Flow CPLDs Mapping FPGAs Only Placing and Routing FPGAs OnlyBitstream Generation FPGAs Only Design Verification 1Verification Tools Verification Type Design Verification 7Three Verification Methods of the Design Flow FPGAs Simulation Back-Annotation 9Back-Annotation Flow for FPGAs Schematic-Based Simulation NetGen HDL-Based Simulation Timing Simulation 11Simulation Points for HDL Designs 2Five Simulation Points in HDL Design Flow UniSim SimPrim Static Timing Analysis FPGAs Only Xilinx Design Download Cables In-Circuit VerificationDesign Rule Checker FPGAs Only Probe Design Size and Performance 3Global Clock Resources Fpga Family Number Destination PinsFpga Design Tips Global Clock Distribution Data Feedback and Clock Enable 12 Gated Clock 13Synchronous Design Using Data Feedback Counters Other Synchronous Design Considerations Q0. . . .Q7 Q8. . . .Q15Q0. . . .Q7Q8. . . .Q15 Tcl Tcl Overview Accessing Help Xilinx Tcl Shell Tcl Fundamentals Tcl Fundamentals Xilinx Tcl Commands 1Xilinx Tcl Commands for General Usage SubcommandsXilinx Namespace Project create and manage projects Tcl Commands for General Usage 2Xilinx Tcl Commands for Advanced Scripting SubcommandsPartition support design preservation Get get partition properties Tcl Commands for General UsageDelete delete a partition Partition delete /stopwatch/Instdcm1 New create a new partition Partition get /stopwatch/Instdcm1 preservePartition new /stopwatch/Instdcm1 Properties list available partition properties Rerun force partition synthesis and implementationPartition properties Set set partition preserve property Process run and manage project processes Run run process task4Process Tasks Clean remove system-generated project files Project cleanProject create and manage projects Getprocesses get project processes Close close the ISE projectGet get project properties Project close Project getprocesses -instance Instdcm1 New create a new ISE projectOpen open an ISE project Project new watchver.ise Properties list project properties Set set project properties, values, and optionsProject properties -process all Project set Map Effort Level high Set device set deviceSet family set device family Project set device xc2vp2 Project set family Virtex2p Set package set device packageSet speed set device speed Project set package fg256 Delete delete timing analysis Timinganalysis generate timing analysis reportsSet top set the top-level module/entity Project set speed Disableconstraints disable timing constraints Disablecpt disable components for path tracing control Stopwatchtiming TSclk=PERIOD TIMEGROUP\sclk\ Enablecpt enable components for path tracing controlTiminganalysis enableconstraints Ns High 50.00000% Timinganalysis enablecpt stopwatchtiming Get get analysis propertyRegsrclk ureg1 ureg2 ureg3 Ascii New new timing analysis Run run analysis Reset reset path filters and constraintsTiminganalysis reset stopwatchtiming Saveas save analysis report Timinganalysis set stopwatchtiming Set set analysis propertiesSetconstraint set constraint for custom analysis Analysisspeed Setendpoints set source and destination endpoints Timinganalysis setconstraint stopwatchtimingPeriod 13 sclk Timinganalysis setfilter stopwatchtiming nets Setquery set up net or timegroup reportSetfilter set filter for analysis Exclude uregnet1 uregnet2 uregnet3 Add add file to project Showsettings generate settings reportXfile manage project files Example Xfile add *.vhd /mysource/mysubdir timing.ucf Get get project file propertiesRemove remove file from project Xfile get timestamp stopwatch.vhd Appendto add objects to a collection Tcl Commands for Advanced ScriptingCollection create and manage a collection Xfile remove stopwatch.vhd Set colVar1 search * -type instance Tcl Commands for Advanced ScriptingCopy copy a collection Set colVar2 $colVar1 Set colVar2 search /top/T* -type instance Equal compare two collectionsSet colVar2 collection copy $colVar1 Collection equal $colVar1 $colVar2 Foreach iterate over elements in a collection Get get collection property Set item collection index $colVar Index extract a collection objectProperties list available collection properties Object name $item Removefrom remove objects from a collection Set set the property for all collectionsCollection properties Collection set displaytype true Object get object informationSizeof show the number of objects in a collection Collection sizeof $colVar Collection foreach obj $colVar set objProps Get get object propertiesName name of the object Object properties $obj foreach prop $objProps Properties list object properties Object name collection index $colVarSet colVar search * -type partition Search search and return matching objects Type type of objectObject type collection index $colVar 6Project Properties Property Name Description Project Properties and OptionsSearch /stopwatch -type instance Option Name Synthesis Tool Project Properties and Options NGDBuild Options Option Name Implementation Tool Option Name Implementation Tool Tcl 10 PAR Options Example Tcl Scripts Sample Tcl Script for General UsageExample Tcl Scripts Tcl Sample Tcl Script for Advanced Scripting 100 PARTGen Syntax PARTGenPARTGen Overview Partgen options PARTGen Options PARTGen Input FilesPARTGen Output Files Arch Print Information for Specified Architecture PARTGen Options Print a List of Devices, Packages, and Speeds PARTGen Options 2s400e Pname Creates Package file and Partlist FilesNopkgfile No Package File Xcv400 Device V400bg432 Part Partlist File Creates Package and Partlist Files Partlist File HeaderDevice Attributes Part architecture family partname diename packagefilename Select RAM PKG File PKG File Done Logical Design Rule Check Logical DRC Overview Net Check Logical DRC ChecksBlock Check Pad Check Clock Buffer Check Name CheckLogical DRC Checks 1Checked Primitive Pins NGD Primitive Pins Checked Primitive Pin Check NGDBuild NGDBuild Overview Converting a Netlist to an NGD File 1NGDBuild Design Flow NGDBuild Syntax NGDBuild SyntaxNGDBuild Input Files Ngdbuild options designname ngdfile.ngd 120 NGDBuild Intermediate Files Add PADs to Top-Level Port SignalsNGDBuild Output Files NGDBuild Options Dd Destination Directory Aul Allow Unmatched LOCsBm Specify BMM Files Ignore UCF File NGDBuild Options InsertkeephierarchyLibraries to Search Synopsys Modular assemble -pimpath pimdirectorypath Modular assemble Module AssemblyModular initial Initial Budgeting of Modular Design Usepimmodulename1 -usepimmodulename2 Modular module -active modulename Modular module Active Module ImplementationNt Netlist Translation Type Pimcreate pimdirectory -ncd designnamerouted.ncd Ignore LOC Constraints Sd Search Specified DirectoryAllow Unexpanded Blocks Verbose Report All Messages Uc User Constraints FileUr Read User Rules File Uc ucffile.ucf 128 MAP MAP Overview MAP Syntax Map options infile.ngd pcffile.pcf MAP Input Files MAP Output FilesMAP Input Files MAP Options 1Map Options and Architectures MAP Options 1Map Options and Architectures Bp Map Slice LogicPack CLBs Cpackfactor Equivalentregisterremoval Remove Redundant Registers Cm Cover ModeDetail Write Out Detailed MAP Report Cm area speed balanced Gf Guide NCD File Gm Guide ModeGm incremental Guide Mode incremental Globalopt Global Optimization Ise ISE Project File Ignorekeephierarchy Ignore Keephierarchy PropertiesIr Do Not Use RLOCs to Generate RPMs Map to Input Functions No logic replication Output File Name Ol Overall Effort Level Olstdmedhigh Registerduplication Duplicate Registers Pr Pack Registers in I/ONo Register Ordering Retiming Register Retiming During Global Optimization Timing Timing-Driven Packing and Placement Tx Transform BusesTx on off aggressive limit Xe Extra Effort Level MAP ProcessDo Not Remove Unused Logic MAP Process Register Ordering Register Ordering Data01 Addr02 Atod03 Dtoa04 Guided Mapping 3Guided Mapping Simulating Map Results Simulating Map Results 4Logical Circuit Representation MAP Report MRP File MAP Report MRP File 148 Development System Reference Guide 149 Type Block GND Xstgnd IOB 152 Halting MAP Halting MAP 154 Physical Design Rule Check DRC Overview DRC Output File DRC SyntaxDRC Input File DRC Options DRC Checks Report Incomplete ProgrammingDRC Checks DRC Errors and Warnings PAR Place and Route Overview PAR Flow Routing PAR ProcessPlacing Timing-driven PAR Command Line Examples Par input.ncd output.ncdPar -k previous.ncd reentrant.ncd pref.pcf Guided PAR Guided PAR PCI Cores PAR Output Files PAR SyntaxPAR Input Files PAR Syntax PAR Options 1Effort Level Options Function Range DefaultGeneral Options Function Range Default Ol value for the router PAR Options 2General Options Function Range Default Guide Options Function Range DefaultExistingfile Execute Commands File Detailed Listing of OptionsGf Guide NCD File Re-Entrant Routing Gm Guide ModeIntstyle Integration Style PAR Options Nopad No Pad Multi-Tasking ModeNumber of PAR Iterations Ol Overall Effort Level Pl Placer Effort Level No PlacementPower Power Aware PAR No Routing Ub Use Bonded I/Os Number of Results to SaveStarting Placer Cost Table Overwrite Existing Files Xe Extra Effort Level Performance Evaluation ModePAR Reports PAR Reports Place and Route Report File Development System Reference Guide 175 Ing score in parenthesis Development System Reference Guide 177 Multi Pass Place and Route Mppr Placer effort levelrouter effort levelcost table numberPar -n 3 -pl high -rl std address.ncd output.dir Guide Reporting Select I/O Utilization and Usage SummaryImporting the PAD File Information Multi Pass Place and Route Mppr Best Performance Mode Xplorer Timing Closure Mode Xplorer SyntaxXplorer Xplorer Options Xplorer Input FilesXplorer Output Files 5Xplorer Options Function Xplorer Report Xplorer 5Xplorer Options Function 184 ReportGen Input Files ReportGenReportGen Syntax ReportGen Output Files Isexflowsilent ReportGen OptionsOption Usage Function Padfmt padcsvtxt Turns Engine PAR Multi-Tasking Option Turns Engine PAR Multi-Tasking OptionTurns Engine Overview Par -m nodefilename -ol high -n 10 mydesign.ncd output.dir Turns Engine Syntax Turns Engine Input Files Turns Engine Output Files LimitationsSystem Requirements Turns Engine Environment Variables Debugging Rsh machinename Screen Output Node Status JOB Time Halting PAR Halting PAR 196 XPower XPower Overview Fpga Designs XPower SyntaxFiles Used by XPower Cpld Designs Using XPower Using XPowerVCD Data Entry Limit Rename Power ReportOther Methods of Data Entry Ls List Supported Devices Tb Turn On Time Based Reporting Specify Settings XML Input FileSpecify VCD file Wx Write XML File Command Line Examples Power ReportsStandard Reports Power Reports Detailed ReportsAdvanced Reports 204 PIN2UCF PIN2UCF Overview PIN2UCF Flow PIN2UCF Output Files PIN2UCF SyntaxPIN2UCF Input Files PIN2UCF Syntax Write to a Report File PIN2UCF OptionsPIN2UCF Scenarios Outfile.ucf Existing Pinlock section. 210 Trace Trace Overview Trce options design.ncd constraint.pcf Trace SyntaxTrace Input Files Trce -runmacro.xtm design.ncd constraint.pcf Trace Output Files Input files to TraceTrace Output Files Advanced Analysis Generate an Error ReportTrace Options Fastpaths Report Fastest Paths Output Timing Report File Name Nodatasheet No Data SheetLimit Timing Report Trace Options Skew Analyze Clock Skew for All Clocks Run Run Timing Analyzer MacroChange Speed Skew Stampstampfile design.ncd Stamp Generates Stamp timing model filesReport Uncovered Paths Ulimit Xml XML Output File Name Trace Command Line ExamplesGenerate a Verbose Report Vlimit Trace Reports Trace Reports Timing Verification with Trace Net Delay ConstraintsPath Delay Constraints Net Skew Constraints Clock Skew and Setup Checking 1Path Delay Constraint Terminology Definition 2Clock Skew and Setup Checking Terminology Terms Definition 2Clock Skew Example 3Clock Passing Through Multiple Buffers Reporting with Trace 5Error reporting for failed timing constraints Data Sheet Report Development System Reference Guide 227 BSLOT0 D0S Guaranteed Setup and Hold Reporting Report Legend Setup Times Hold Times Summary Report Without a Physical Constraints File Specified Trce -o summary.twr ramb16s1.ncd Trce -o summary1.twr ramb16s1.ncd clkperiod.pcf Development System Reference Guide 233 Trce -e 3 ramb16s1.ncd clkperiod.pcf -o errorreport.twr Development System Reference Guide 235 236 Development System Reference Guide 237 BUFGMUX.I0 Offset Constraints Offset Constraints Offset in Constraint Examples Offset in HeaderOffset in Path Details Offset in Detailed Path Data Offset In with Phase Shifted Clock Offset in Detail Path Clock Path Development System Reference Guide 243 Offset OUT Constraint Examples Offset OUT Header Offset OUT Path Details Offset OUT Detail Clock Path Offset OUT Detail Path Data Period Header Period ConstraintsPeriod Constraints Examples Period Constraints Period Path Period Path Details Period Constraint with Phase Period Path with Phase Halting Trace Minimum Period Statistics Speedprint Speedprint Overview Speedprint Options Specify TemperatureSpeedprint Syntax Min Display Minimum Speed Data Command Description Speedprint Example CommandsSpeedprint Example Commands Speedprint Example Reports Lvttl Fast BitGen BitGen Overview BitGen Syntax Option Output FileLoutfilename.ll Moutfilename.msk Boutfilename.rbt BitGen Input Files BitGen Output FilesBitGen Input Files BitGen Options Create Rawbits File Bitgen -goptionsetting design.ncd design.bit design.pcf Bd Update Block RamsSet Configuration Do Not Run DRC Binary ActiveReconfigActivateGCLK CclkPin ConfigRate Compress DCIUpdateMode DCMShutdownDebugBitstream DonePin DisableBandgapDONEcycle DonePipe Gclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 DriveDoneEncrypt GSRcycle HswapenPin GWEcycleGTScycle Key0, Key1, Key2, Key3, Key4, Key5 LCKcycle KeyFileKeyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5 M0Pin Matchcycle M1PinM2Pin PartialGCLK PartialRight PartialMask0, PartialMask1, PartialMask2PartialLeft Persist ReadBack PowerdownPinProgPin Security StartKey SEURepairStartCBC StartupClk TdoPin TckPinTdiPin TmsPin No BIT File UnusedPinUserID Create a Partial Bit File Create a Logic Allocation FileGenerate a Mask File Overwrite Existing Output File 276 BSDLAnno BSDLAnno Overview BSDLAnno Output Files BSDLAnno SyntaxBSDLAnno Input Files BSDLAnno Options Generic Parameter BSDLAnno File CompositionEntity Declaration BSDLAnno File Composition Logical Port Description Package Pin-Mapping USE Statement Scan Port IdentificationTAP Description Bsdl File Modifications for Single-Ended Pins Boundary Register Description Explanation Header Comments Boundary Scan Behavior in Xilinx DevicesModifications to the Designwarning Section BSDLAnno BSDLAnno version number PROMGen PROMGen Overview PROMGen Output Files PROMGen SyntaxPROMGen Input Files Promgen options PROMGen Options Load Prom File Add BIT FIlesProm Format File1.bit file2.bit Load Upward Prom SizeTemplate File Ver Version Enable Compression Bit Swapping in Prom Files PROMGen Examples PROMGen Examples 292 IBISWriter IBISWriter Overview IBISWriter Syntax Ibiswriter options infile outfile.ibs IBISWriter Options IBISWriter Input FilesIBISWriter Output Files Set Reference Voltage Ml Multilingual Support Architecture Option Value Description Pin Generate Package Parasitics IBISWriter Options 298 CPLDfit CPLDfit Overview CPLDfit Syntax CPLDfit Input FilesCPLDfit Output Files CPLDfit Options Keepio Prevent Optimization of Unused Inputs Inputs Number of Inputs to Use During OptimizationIostd Specify I/O Standard Loc Keep Specified Location Constraints Nogsropt Disable Global Set/Reset Optimization Nofbnand Disable Use of Foldback NandsNogclkopt Disable Global Clock Optimization Nogtsopt Disable Global Output-Enable Optimization Specify Xilinx Part Power Set Power ModeOptimize Optimize Logic for Density or Speed Pinfbk Use Pin Feedback Slew Set Slew Rate Terminate Set to Termination ModeUnused Set Termination Mode of Unused I/Os Wysiwyg Do Not Perform Optimization 306 Tsim Tsim Syntax Tsim Input Files TAEngine TAEngine Overview TAEngine Syntax 1TAEngine Design Flow Iopath Trace Paths TAEngine OptionsDetail Detail Report Specify Output Filename 312 Hprep6 1Hprep6 Design Flow Hprep6 Syntax Hprep6 OptionsAutosig Automatically Generate Signature Produce ISC File Nopullup Disable PullupsSpecify Signature Value for Readback Tmv Specify Test Vector File 316 NetGen NetGen Overview NetGen 1NetGen Output File Types Input Design File NetGen Supported Flows NetGen Simulation FlowNetGen Functional Simulation Flow NetGen Simulation Flow Output files for NetGen Functional Simulation NetGen Timing Simulation FlowSyntax for NetGen Functional Simulation Ngcbuildoptions toplevelnetlistfile outputngcfile Syntax for NetGen Timing Simulation Fpga Timing SimulationNetGen Timing Simulation Flow Input files for Cpld Timing Simulation Output files for Fpga Timing SimulationCpld Timing Simulation Output files for Cpld Timing Simulation Options for NetGen Simulation Flow Insertppbuffers Insert Path Pulse Buffers Mhf Multiple Hierarchical FilesModule Simulation of Active Module Change Speed Ofmt Output FormatPcf PCF File Sim Generate Simulation Netlist Tp Bring Out Global 3-State Net as Port Ti Top Instance NameTm Top Module Name Insertglbl Insert glbl.v Module Sdfanno Include $sdfannotate Ne No Name EscapingPf Generate PIN File Sdfpath Full Path to SDF File VHDL-Specific Options for Functional and Timing Simulation NetGen Equivalence Checking Flow NetGen Equivalence Checking FlowXon Select Output Behavior for Timing Violations Xon truefalse Syntax for NetGen Equivalence Checking Input files for NetGen Equivalence Checking Output files for NetGen Equivalence Checking Options for NetGen Equivalence Checking FlowEcn Equivalence Checking Module Verification of Active Module NetGen Static Timing Analysis Flow Ngm Design Correlation FileNetGen Static Timing Analysis Flow Input files for Static Timing Analysis Output files for Static Timing AnalysisSyntax for NetGen Static Timing Analysis Options for NetGen Static Timing Analysis Flow 336 Preserving and Writing Hierarchy Files Preserving and Writing Hierarchy FilesSta Generate Static Timing Analysis Netlist Modulename .sim Modulename .ecn Modulename .sta Dedicated Global Signals in Back-Annotation Simulation Testbench FileHierarchy Information File Global Signals in Verilog Netlist Global Signals in Vhdl NetlistDedicated Global Signals in Back-Annotation Simulation 340 Xflow Xflow Overview Xflow Syntax 1XFLOW Design Flow Xflow Input Files Xflow Input Files Xflow Output Files Xflow Output Files 1XFLOW Output Files FPGAs and CPLDs 2XFLOW Output Files FPGAs Xflow Flow Types Assemble Module AssemblyXflow Flow Types 3XFLOW Output Files CPLDs Ecn Create a File for Equivalence Checking Config Create a BIT File for FPGAsConfigoptionfile 4Option Files for -assemble Flow Type Description 5Option Files for -ecn Flow Type Description Fit Fit a CpldFsim Create a File for Functional Simulation 6Option Files for -fit Flow Type Description Xflow -p xc2v250fg256-5 -fsim genericverilog.opt testclk.v Implement Implement an Fpga7Option Files for -fsim Flow Type Implement optionfile Initial budget.opt Initial Initial Budgeting of Modular DesignXflow Flow Types 8Option Files for -implement Flow Type Xflow -p xc2v250fg256-5 -initial budget.opt top.edf Module Active Module Implementation Moduleoptionfile -activemodulename9Option Files for -module Flow Type 10Option Files for -mppr Flow Type Description Mppr Multi-Pass Place and Route for FPGAsSta Create a File for Static Timing Analysis 11Option Files for -sta Flow Type Description Synth Synthesis TypesSynthoptionfile 12Option Files for -synth Flow Type Description Tsim Create a File for Timing SimulationOption Files for -synth Flow Types Testclk.prj Flow Files 13Option Files for -tsim Flow Type Description Flow File Format Fpga Exports Flag Enabled DisabledTriggers Reports User Command Blocks End Program programname Xflow Option Files Option File Format Ed Copy Files to Export Directory Xflow OptionsActive Active Module Specify a Global Variable Ooutputfilename Norun Creates a Script File OnlyChange Output File Name Xflow -implement balanced.opt -o newname testclk.edf Pdpimdirectory Pd PIMs DirectoryRd Copy Report Files Rdreportdirectory Wd Specify a Working Directory Using Xflow Flow Types in CombinationRunning Xflow Running Smart Flow Using the SCR, BAT, or TCL File Using the Xilxflowpath Environment VariableRunning Xflow 366 Data2MEM Data2MEM Overview Block RAM Memory Map .bmm files Data2MEM SyntaxData2MEM Input and Output Files Executable and Linkable Format .elf files Bit .bit files Debugging Information Format Dwarf .drf filesMemory .mem files Verilog .v files Vhdl .vhd files 1Data2MEM Command Line Options DescriptionData2MEM Options UCF .ucf files Data2MEM Options 1Data2MEM Command Line Options Pp filename Xilinx Development System Files Name Type Produced By Description Appendix MOD Ascii Trace NKY TCL Ascii 378 EDIF2NGD, and NGDBuild EDIF2NGD EDIF2NGD Design Flow EDIF2NGD Output Files EDIF2NGD SyntaxEDIF2NGD Input Files Edif2ngd options ediffile ngofile Add PADs to Top-Level Port Signals EDIF2NGD OptionsAul Allow Unmatched LOCs Ignore LOC Constraints Libraries to SearchPart Number Llibname NGDBuild NGDBuild and the Netlist Readers NGDBuild Bus Naming Conventions Netlist Launcher NetlisterBus Matching Busnameindex DI3 Netlist Launcher Netlister User Rules and System Rules Netlist Launcher Rules FilesUser Rules File User Rules Format Development System Reference Guide 389 System Rules File Value Types in Key Statements Rules File Examples Example 1 Edfrule System Rule Example 2 User Rule Example 3 User Rule NGDBuild File Names and Locations Example 4 User RuleNGDBuild File Names and Locations 394 Glossary Abel Asic Bonded BitstreamBlock Boundary scan Buft CAE CLB Cmos Combinatorial logic ConfigurationContention Compiler Dangling bus CpldDaisy chain Dangling net DRC DSP EDA Edif Eprom FdsdFifo Fmap Fpga Global buffers Global Set/Reset netGate array Global 3-state net HDL Ibuf Ieee IFD Jedec LSB MSB NCD NGM PAL PIM PLD Prom RAM ROM RPMRTL Signal SDF standard delay formatSet/reset Startup symbol TCL Trace Tsim TTL Vital WireVhdl Xtclsh 422