Number of Results to Save, Starting Placer Cost Table

Chapter 9: PAR

–s (Number of Results to Save)

–snumber_to_save –niterations

The –s option is used with the –n option to save the number of results that you specify. By default (with no –s option), all results are saved. The valid range for the number_to_save is 1–100.

The –s option compares the results of each iteration and saves the best output NCD files. The best NCDs are determined by a score assigned to each output design. This score takes into account such factors as the number of unrouted nets, the delays on nets and conformance to any timing constraints. The lower the score, the better the design. This score is described in the PAR Reports section of this chapter. See the Multi Pass Place and Route (MPPR) section for more details.

par -s 2 -n 10 -pl high -rl std design.ncd output_directory design.pcf

–t (Starting Placer Cost Table)

–tplacer_cost_table

When the -n option is specified without the -t option, PAR starts at placer cost table 1.The –t option specifies the cost table at which the placer starts (placer cost tables are described in “Placing”). If the cost table 100 is reached, placement begins at 1 again, if you are running MPPR due to the –n options. The placer_cost_table range is 1–100, and the default is 1.

par –t 10 –s 1 –n 5 –pl high –rl std design.ncd output_directory design.pcf

The previous option is often used with MPPR to try out various cost tables. In this example, cost table 10 is used and a MPPR run is performed for 5 iterations. The par run starts with cost table 10 and runs through 14. The placer effort is at the highest and the router effort at std. The number of NCD saved will be the best one.

Note: See the Multi Pass Place and Route (MPPR) section for more details.

–ub (Use Bonded I/Os)

par –ub design.ncd output.ncd design.pcf

By default (without the -ub option), I/O logic that MAP has identified as internal can only be placed in unbonded I/O sites. If the –ub option is specified, PAR can place this internal I/O logic into bonded I/O sites in which the I/O pad is not used. The option also allows PAR to route through bonded I/O sites. If you use the –ub option, make sure this logic is not placed in bonded sites connected to external signals, power, or ground. You can prevent this condition by placing PROHIBIT constraints on the appropriate bonded I/O sites. See the Constraints Guide for more information on constraints.

–w (Overwrite Existing Files)

par input.ncd –w existing_NCD.ncd input.pcf

Use the –w option to instruct PAR to overwrite existing output files, including the input design file if it follows the –w option. The default is not to overwrite an NCD. Therefore if the given NCD exists, then PAR gives an error and terminates before running place and route.

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Development System Reference Guide

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i manual Number of Results to Save, Starting Placer Cost Table, Ub Use Bonded I/Os

Models: 8.2i