Run Run Timing Analyzer Macro, Change Speed, Skew

Chapter 12: TRACE

–run (Run Timing Analyzer Macro)

–runmacro.xtm [design.ncd] [constraints.pcf]

Commands used to generate custom timing reports with Timing Analyzer can be saved in a macro file and run in batch mode with the TRACE program. The –run option uses a Timing Analyzer macro file (XTM) to produce timing reports based on the commands specified in the XTM file. The –run option also generates a log file (macro_file.log) that lists all of the Timing Analyzer macro commands and any status messages.

Optional design and PCF files can be specified on the command line and will be opened before TRACE runs the XTM macro file. If a design is not specified on the command line, the XTM file must include the macro command to open a design. If an output report filename and type are not specified in the macro file, TRACE generates an XML timing report (TWX) file by default and names the report Timing1.twx. When multiple timing reports and generated by the macro file, TRACE uses the same naming convention: Timing1.twx, Timing2.twx, Timing3.twx, and so on.

Note: For information on creating an XTM macro file, see the Timing Analyzer online help.

–s (Change Speed)

–s[speed]

The –s option overrides the device speed contained in the input NCD file and instead performs an analysis for the device speed you specify. The –s option applies to whichever report type you produce in this TRACE run. The option allows you to see if faster or slower speed grades meet your timing requirements.

The device speed can be entered with or without the leading dash. For example, both –s 3 and –s–3are valid entries.

Some architectures support minimum timing analysis. The command line syntax for min timing analysis is: trace –s min. Do not place a leading dash before min.

Note: The –s option only changes the speed grade for which the timing analysis is performed; it does not save the new speed grade to the NCD file.

–skew (Analyze Clock Skew for All Clocks)

–skew

This option is obsolete. By default, TRACE now analyzes clock skew and hold time violations for all clocks, including those using general clock routing resources.

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Development System Reference Guide

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Xilinx 8.2i Run Run Timing Analyzer Macro, Change Speed, Skew Analyze Clock Skew for All Clocks

Models: 8.2i