Xilinx 8.2i manual Nky

Appendix :

R

	Name	Type		Produced By	Description
	NGO	Data		Netlist Readers	File containing a logical description
					of the design in terms of its original
					components and hierarchy
	NKY	Data		BitGen	Encryption key file
	NLF	ASCII		NetGen	NetGen log file that contains
					information on the NetGen run
	NMC	Binary		FPGA Editor	Xilinx physical macro library file
					containing a physical macro
					definition that can be instantiated
					into a design
	OPT	ASCII		XFLOW	Options file used by XFLOW
	PAD	ASCII		PAR	File containing a listing of all
					I/O components used in the design
					and their associated primary pins
	PAR	ASCII		PAR	PAR report file containing
					execution information about the
					PAR command run. The file shows
					the steps taken as the program
					converges on a placement and
					routing solution
	PCF	ASCII		MAP, FPGA Editor	File containing physical constraints
					specified during design entry (that
					is, schematics) and constraints
					added by the user
	PIN	ASCII		NetGen	Cadence signal-to-pin mapping file
	PRM	ASCII		PROMGen	File containing a memory map of a
					PROM file showing the starting
					and ending PROM address for each
					BIT file loaded
	RBT	ASCII		BitGen	“Rawbits" file consisting of ASCII
					ones and zeros representing the
					data in the bitstream file
	RPT	ASCII		PIN2UCF	Report file generated by PIN2UCF
					when conflicting constraints are
					discovered. The name is
					pinlock.rpt.
	RCV	ASCII		FPGA Editor	FPGA Editor recovery file
	SCR	ASCII		FPGA Editor or	FPGA Editor or XFLOW command
				XFLOW	script file
	SDF	ASCII		NetGen	File containing the timing data for a
					design. Standard Delay Format File
	SVF	ASCII		NetGen	Assertion file written for Formality
					equivalency checking tool
376			www.xilinx.com		Development System Reference Guide