R

Netlist Launcher (Netlister)

Following are the keys allowed and the values expected:

Note: The value types for the keys are described in “Value Types in Key Statements”.

•RuleName—This key identifies the beginning of a rule. It is also used in error messages relating to the rule. It expects a RULENAME value. A value is required.

•NetlistFile—This key specifies a netlist or class of netlists that the netlist reader takes as input. The extension of NetlistFile is used together with the TargetExtension to identify the rule. It expects either a FILENAME or an EXTENSION value. If a file name is specified, it should be just a file name (that is, no path). Any leading path is ignored. A value is required.

•TargetExtension—This key specifies the class of files generated by the netlist reader. It is used together with the extension from NetlistFile to identify the rule. It expects an EXTENSION value. A value is required.

•Netlister—This key specifies the netlist reader to use when translating a specific netlist or class of netlists to a target file. The specific netlist or class of netlists is specified by NetlistFile, and the class of target files is specified by TargetExtension. It expects an EXECUTABLE value. A value is required.

•NetlisterTopOptions—This key specifies options for the netlist reader when compiling the top-level design. It expects an OPTIONS value or the keyword NONE. Included in this string should be the keywords $INFILE and $OUTFILE, in which the input and output files is substituted. In addition, the following keywords may appear.

♦$PART—The part passed to NGDBuild by the –p option is substituted. It may include architecture, device, package and speed information. The syntax for a $PART specification is the same as described in “–p (Part Number)” in Chapter 1.

♦$FAMILY—The family passed to NGDBuild by the –p option is substituted. A value is optional.

♦$DEVICE—The device passed to NGDBuild by the –p option is substituted. A value is optional.

♦$PKG—The package passed to NGDBuild by the –p option is substituted. A value is optional.

♦$SPEED—The speed passed to NGDBuild by the –p option is substituted. A value is optional.

♦$LIBRARIES—The libraries passed to NGDBuild. A value is optional.

♦$IGNORE_LOCS—Substitute the –r option to EDIF2NGD if the NGDBuild command line contained a –r option.

♦$ADD_PADS—Substitute the –a option to EDIF2NGD if the NGDBuild command line contained a –a option.

The options in the NetlisterTopOptions line must be enclosed in quotation marks.

•NetlisterOptions—This key specifies options for the netlist reader when compiling sub-designs. It expects an OPTIONS value or the keyword NONE. Included in this string should be the keywords $INFILE and $OUTFILE, in which the input and output files is substituted. In addition, any of the keywords that may be entered for the NetlisterTopOptions key may also be used for the NetlisterOptions key.

The options in the NetlisterOptions line must be enclosed in quotation marks.

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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.
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