Xilinx 8.2i manual Simulation, Back-Annotation

Chapter 2: Design Flow

R

The following figure shows the verification methods of the design flow for CPLDs.

Simulation

Input Stimulus

Simulation

Simulation Netlist

Translate to

Simulator Format

Basic Design Flow

Integrated Tool

Design Entry

Functional Simulator

Paths

Translate to	NGD
Simulator Format

Optimization and

Fitting

Static Timing

Timing Simulation Path

Translation VM6

Programming

File Creation

Back-Annotation

JED

NGA

Xilinx CPLD

Static Timing Analysis

In-Circuit Verification

In-Circuit Verification

X9538

Figure 2-8:Three Verification Methods of the Design Flow (CPLDs)

Simulation

You can run functional or timing simulation to verify your design. This section describes the back-annotation process that must occur prior to timing simulation. It also describes the functional and timing simulation methods for both schematic and HDL-based designs.

Back-Annotation

Before timing simulation can occur, the physical design information must be translated and distributed back to the logical design. For FPGAs, this back-annotation process is done with a program called NetGen. For CPLDs, back-annotation is performed with the TSim Timing Simulator. These programs create a database, which translates the back-annotated information into a netlist format that can be used for timing simulation.

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