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Xilinx 8.2i manual Xplorer Input Files, Xplorer Output Files, 5Xplorer Options Function

Models: 8.2i

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Chapter 9: PAR

R

options can be any number of the Xplorer options listed in “Xplorer Options.” Use the -clk option for Best Performance Mode and the -uc option for Timing Closure Mode. Separate multiple options with spaces.

part_name is the complete name of the Xilinx part, specified with the –p option.

Note: You can also run Xplorer from the Xilinx TCL Shell, accessible through the TCL Console tab in Project Navigator.

Xplorer Input Files

Input to Xplorer consists of the following files:

•EDIF—netlist file produced by synthesis.

•NGC—netlist file produced by XST.

Xplorer Output Files

Output from Xplorer consists of following:

RPT—report file that summarizes all of the results from the Xplorer runs. The best run is identified at the end of the report file. See “Xplorer Report” in this chapter for additional information.

LOG—log files that contain all standard out messages. Xplorer produces two log files: xplorer.log and run.log.

run<1>.*—multiple log files with execution details for each Xplorer run. File names are based on the individual Xplorer run; for example, run1.log, run1.ucf, run 2.log, run2.ucf.

Xplorer Options

The following table lists the Xplorer command line options, along with a short description of each option.

Table 9-5:Xplorer Options

Option

Function

 

 

–bm <bmm_file_name>

Specifies the BMM file name for block RAM initialization.

 

 

–clk <clock_name>

Specifies the name of the clock net you wish to optimize in

 

Best Performance Mode. If the –clk option is omitted, the

 

script will use the timespec defined in the User

 

Constraints File (UCF).

 

 

–freq <value_in_MHz>

Specifies the first attempted frequency in Best

 

Performance Mode. The starting value impacts the

 

number of runs. Without this option, the script

 

determines a good starting value.

 

 

–map_options <option(s)>

Specifies additional MAP options to use during the

 

Xplorer runs. See “MAP Options” in Chapter 7 for a

 

complete list of MAP options. Separate multiple options

 

with spaces.

 

 

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Xilinx 8.2i manual Xplorer Input Files, Xplorer Output Files, 5Xplorer Options Function
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8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.