Xilinx 8.2i manual Offset in Detail Path Clock Path, Offset In with Phase Shifted Clock

Chapter 12: TRACE

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OFFSET IN Detail Path Clock Path

The second section is the clock path. In this example the clock starts at an IOB, goes to a DCM, comes out CLK0 of the DCM through a global buffer (BUFGHUX). It ends at a clock pin of a FF.

The Tdcmino is a calculated delay. This is the equation:

Clock Path: wclk_in to wr_addr[2]
Location	Delay type	Delay(ns) Logical Resource(s)
-------------------------------------------------			----------------
D7.I	Tiopi	0.825	wclk_in
			write_dcm/IBUFG
DCM_X0Y1.CLKIN	net (fanout=1)	0.798	write_dcm/IBUFG
DCM_X0Y1.CLK0	Tdcmino	-4.297 write_dcm/CLKDLL
BUFGMUX3P.I0	net (fanout=1)	0.852	write_dcm/CLK0
BUFGMUX3P.O	Tgi0o	0.589	write_dcm/BUFG
SLICE_X3Y11.CLK	net (fanout=41)	0.748	wclk
-------------------------------------------------			----------------
Total		-0.485ns (-2.883ns logic,
2.398ns route)

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OFFSET In with Phase Shifted Clock

In the following example, the clock is the CLK90 output of the DCM. The clock arrival time is 2.5 ns. The rclk_90 rising at 2.500 ns. This number is calculated from the PERIOD on rclk_in which is 10ns in this example. The 2.5 ns affects the slack. Because the clock is delayed by 2.5 ns, the data has 2.5 ns longer to get to the destination.

If this path used the falling edge of the clock, the destination clock would say, falling at 00 ns 7.500 ns (2.5 for the phase and 5.0 for the clock edge). The minimum allowable offset can be negative because it is relative to the initial edge of the clock. A negative minimum allowable offset means the data can arrive after the initial edge of the clock. This often occurs when the destination clock is falling while the initial edge is defined as rising. This can also occur on clocks with phase shifting.

Example:

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Timing constraint: OFFSET = IN 4 nS BEFORE COMP "rclk_in" ;

2 items	analyzed,	0 timing errors detected.
Minimum	allowable	offset is 1.316ns.

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