Xilinx 8.2i manual Xilinx Development System Files, Name Type Produced By Description

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Appendix A

Xilinx Development System Files

This appendix gives an alphabetic listing of the files used by the Xilinx development system.

Name	Type	Produced By	Description
BIT	Data	BitGen	Download bitstream file for
			devices containing all of the
			configuration information from the
			NCD file
BGN	ASCII	BitGen	Report file containing information
			about a BitGen run
BLD	ASCII	NGDBuild	Report file containing information
			about an NGDBuild run, including
			the subprocesses run by NGDBuild
DATA	C File	TRCE	File created with the –stamp option
			to TRCE that contains timing
			model information
DC	ASCII	Synopsys FPGA	Synopsys setup file containing
		Compiler	constraints read into the Xilinx
			Development System
DLY	ASCII	PAR	File containing delay information
			for each net in a design
DRC	ASCII	BitGen	Design Rule Check file produced
			by BitGen
EDIF (various	ASCII	CAE vendor’s EDIF 2	EDIF netlist. The Xilinx
file extensions)		0 0 netlist writer.	Development System accepts an
			EDIF 2 0 0 Level 0 netlist file
EDN	ASCII	NGD2EDIF	Default extension for an EDIF
			2 0 0 netlist file
ELF	ASCII	Used for NetGen	This file populates the Block RAMs
			specified in the .bmm file.

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