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Xilinx 8.2i manual Input files for Static Timing Analysis, Output files for Static Timing Analysis

Models: 8.2i

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Chapter 22: NetGen

R

The figure below illustrates the NetGen Static Timing Analysis flow.

NCDPCF

 

NetGen

V/SDF

STA

 

Library

Static Timing Analysis Tool

X10252

Figure 22-6:Static Timing Analysis Flow for FPGAs

Input files for Static Timing Analysis

The Static Timing Analysis flow uses the following files as input:

•NCD file—This physical design file may be mapped only, partially or fully placed, or partially or fully routed.

•PCF (optional)—This is a physical constraints file. If prorated voltage and temperature is applied to the design, the PCF file must be included to pass this information to NetGen. See “–pcf (PCF File)” for more information.

Output files for Static Timing Analysis

The Static Timing Analysis flow uses the following files as output:

•SDF file—This SDF 3.0 compliant standard delay format file contains delays obtained from the input file.

•Verilog (.v) file—This is a IEEE 1364-2001 compliant Verilog HDL file that contains the netlist information obtained from the input file. This file is a timing simulation model and cannot be synthesized or used in any manner other than for static timing analysis. This netlist uses simulation primitives, which may not represent the true implementation of the device. The netlist represents a functional model of the implemented design.

Syntax for NetGen Static Timing Analysis

The following command runs the NetGen Static Timing Analysis flow:

netgen -stainput_file[.ncd]

The input_file is the input file name and extension.

To get help on command line usage for equivalence checking, type:

netgen -h sta

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Xilinx 8.2i manual Input files for Static Timing Analysis, Output files for Static Timing Analysis
Page 333 Page 335

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.