Xilinx 8.2i manual Period Constraint with Phase

Chapter 12: TRACE

R

At the end of the path is the total amount of the delay followed by a break down of logic vs routing. This is useful information for debugging a timing failure. For more information see Timing Improvement Wizard for suggestions on how to fix a timing issues.

Example:

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Constraints Improvement Wizard

Data Path: wr_addr[0] to fifo_ram/BU5/SP

Location	Delay type	Delay(ns) Logical Resource(s)
-------------------------------------------------				---------------
SLICE_X2Y4.YQ	Tcko		0.568	wr_addr[0]
SLICE_X6Y8.WF1	net (fanout=112)		2.721	wr_addr[0]
SLICE_X6Y8.CLK	Tas		0.522	fifo_ram/BU5/SP
-------------------------------------------------				---------------

Total	3.811ns (1.090ns logic,
2.721ns route)
	(28.6% logic, 71.4% route)

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PERIOD Constraint with PHASE

This is a PERIOD constraint for a clock with Phase. It is a constraint created by the Translate (ngdbuild) step. It is related back to the TS_rclk constraint with a PHASE of 2.5 ns added. The clock is the CLK90 output of the DCM. Since the PERIOD constraint is 10 ns the clock phase from the CLK90 output is 2.5 ns, one-fourth of the original constraint. This is defined using the PHASE keyword.

Example:

Timing constraint: TS_rclk_90_dcm = PERIOD TIMEGRP "rclk_90_dcm"

TS_rclk * 1.000000 PHASE + 2.500

nS HIGH 50.000 % ;

6 items analyzed, 1 timing error detected.

Minimum period is 21.484ns.

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