Global Signals in Verilog Netlist

Dedicated Global Signals in Back-Annotation Simulation

Global Signals in Verilog Netlist

For Verilog, the glbl module is used to model the default behavior of global the GSR and GTS. The glbl.GSR and glbl.GTS can be directly referenced as global GSR/GST signals anywhere in a design or in any library cells.

NetGen writes out the glbl module definition in the output Verilog netlist. For a non- hierarchical design or a single-file hierarchical design, this glbl module definition is written at the bottom of the netlist. For a single-file hierarchical design, the glbl module is defined inside the top-most module. For a multi-file hierarchical design (-mhf option), NetGen writes out glbl.v as a hierarchical module.

If the GSR and GTS are brought out to the top-level design as ports using the -gp and -tp options, the top-most module has the following connectivity:

glbl.GSR = GSR_PORT

glbl.GTS = GTS_PORT

The GSR_PORT and GTS_PORT are ports on the top-level module created with the -gp and -tp options. If a STARTUP block is used in the design, the STARTUP block is translated to buffers that preserve the intended connectivity of the user-controlled signals to the global GSR and GTS (glbl.GSR and glbl.GTS).

When there is a STARTUP block in the design, the STARTUP block hierarchical level is always preserved in the output netlist. The output of STARTUP is connected to the global GSR/GTS signals (glbl.GSR and glbl.GTS).

For all hierarchical designs, the glbl module must be compiled and referenced along with the design. For information on setting the GSR and GTS for FPGAs, see the “Simulating Verilog” section in the Synthesis and Simulation Design Guide.

Global Signals in VHDL Netlist

Global signals for VHDL netlists are GSR and GTS, which are declared in the library package Simprim_Vcomponents.vhd. The GSR and GTS can be directly referenced anywhere in a design or in any library cells.

The X_ROC and X_TOC components in the VHDL library model the default behavior of the GSR and GTS. If the -gp and -tp options are not used, NetGen instantiates X_ROC and X_TOC in the output netlist. Each design has only one instance of X_ROC and X_TOC. For hierarchical designs, X_ROC and X_TOC are instantiated in the top-most module netlist.

X_ROC and X_TOC are instantiated as shown below:

X_ROC (O => GSR);

X_TOC (O => GTS);.

If the GSR and GTS are brought out to the top-level design using the -gp and -tp options, There will be no X_ROC or X_TOC instantiation in the design netlist. Instead, the top-most module has the following connectivity:

GSR<= GSR_PORT

GTS<= GTS_PORT

The GSR_PORT and GTS_PORT are ports on the top-level module created with the -gp and -tp options.

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8.2i specifications

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Xilinx 8.2i manual Global Signals in Verilog Netlist, Global Signals in Vhdl Netlist

Models: 8.2i

Dedicated Global Signals in Back-Annotation Simulation

Global Signals in Verilog Netlist

Global Signals in VHDL Netlist

8.2i specifications