Design Verification

Chapter 2: Design Flow

Design verification is testing the functionality and performance of your design. You can verify Xilinx designs in the following ways:

•Simulation (functional and timing)

•Static timing analysis

•In-circuit verification

The following table lists the different design tools used for each verification type.

Table 2-1:Verification Tools

Verification Type	Tools

Simulation	Third-party simulators (integrated and
	non-integrated)

Static Timing	TRACE (command line program)
Analysis	Timing Analyzer (GUI)
	Timing Analyzer (GUI)
	Mentor Graphics® TAU and Innoveda
	BLAST software for use with the STAMP
	file format (for I/O timing verification
	only)

In-Circuit Verification	Design Rule Checker (command line
	program)
	Download cable

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Development System Reference Guide

Page 40

Image 40

Xilinx 8.2i manual Design Verification, 1Verification Tools Verification Type

8.2i specifications

Xilinx 8.2i is a significant version of the Xilinx ISE (Integrated Software Environment) that emerged in the early 2000s, marking an important milestone in the world of FPGA (Field-Programmable Gate Array) development. This version introduced a slew of advanced features, technologies, and characteristics that made it an indispensable tool for engineers and developers in designing, simulating, and implementing digital circuits.

One of the standout features of Xilinx 8.2i is its enhanced design entry capabilities. This version supports multiple design entry methods, including schematic entry, VHDL, and Verilog HDL, giving engineers the flexibility to choose their preferred approach. The integrated environment provides user-friendly graphical interfaces, making it accessible for both novice and experienced users.

Xilinx 8.2i's synthesis tools have been improved to enable more efficient design compilation and optimization. The new algorithms used in this version facilitate faster synthesis times while reducing power consumption and improving performance. Furthermore, it features support for advanced FPGA architectures, which allows for the implementation of more complex designs with greater efficiency.

The implementation tools in Xilinx 8.2i include advanced place and route capabilities, utilizing state-of-the-art algorithms for optimized resource usage. These tools enable designers to make better use of FPGA resources, ensuring that designs fit within the constraints of the target device while maximizing performance.

Another key characteristic of Xilinx 8.2i is its extensive support for various Xilinx devices such as the Spartan, Virtex, and CoolRunner series. This compatibility ensures that developers can leverage the powerful features of these FPGA families, including high-speed transceivers and DSP slices.

Xilinx 8.2i also places a strong emphasis on simulation and verification. The version integrates with various simulation tools, allowing for thorough testing of the designs before implementation. This reduces the risk of errors and ensures that the final product meets specifications.

In addition, this version includes support for design constraints, enabling engineers to specify timing, area, and other critical design parameters. By accommodating constraints, Xilinx 8.2i helps in achieving reliable and efficient designs tailored to project needs.

In summary, Xilinx 8.2i is a robust software development tool that enhances the design process for FPGAs. Its comprehensive features, including multiple design entry options, advanced synthesis and implementation tools, extensive device support, and strong simulation capabilities, make it a valuable resource for engineers and developers striving for innovation in digital design.

Contents

Development System Reference Guide Development System Reference Guide Guide Contents About This Guide Preface About This Guide Conventions Additional ResourcesTypographical Online Document Preface About This Guide Convention Meaning or Use ExampleAllow block blockname Loc1 loc2 ... locn Table of Contents Tcl PARTGen NGDBuild Logical Design Rule CheckMAP Physical Design Rule Check PAR Development System Reference Guide XPower PIN2UCF Trace Trace Output Files Speedprint BitGen BSDLAnno PROMGen IBISWriter Tsim CPLDfitTAEngine Hprep6 NetGen Development System Reference Guide Xflow Data2MEM EDIF2NGD, and NGDBuild 1Command Line Programs in the Design Flow Design Flow Step Command Line Program OverviewIntroduction Command Line Syntax Command Line OptionsExecute Commands File Introduction Symbol Description Command Line OptionsHelp Introduction Symbol Description Intstyle Integration StyleProgramname -harchitecturename Programname -h filename 2Part Number Examples Specification Part Number Invoking Command Line Programs Introduction 2Part Number Examples Specification Design Flow Design Flow Overview Design Flow Xilinx Design Flow Design Flow Overview 2Xilinx Software Design Flow FPGAs 3Xilinx Software Design Flow CPLDs Hierarchical Design Design Entry and SynthesisDesign Entry and Synthesis Library Elements Schematic Entry OverviewCore Generator Tool FPGAs Only HDL Entry and Synthesis Functional SimulationConstraints Mapping Constraints FPGAs Only Block Placement Timing SpecificationsDesign Implementation Netlist Translation Programs Design Implementation 5Design Implementation Flow FPGAs 6Design Implementation Flow CPLDs Placing and Routing FPGAs Only Mapping FPGAs OnlyBitstream Generation FPGAs Only Design Verification 1Verification Tools Verification Type Design Verification 7Three Verification Methods of the Design Flow FPGAs Simulation Back-Annotation 9Back-Annotation Flow for FPGAs Schematic-Based Simulation NetGen HDL-Based Simulation Timing Simulation 11Simulation Points for HDL Designs 2Five Simulation Points in HDL Design Flow UniSim SimPrim Static Timing Analysis FPGAs Only In-Circuit Verification Design Rule Checker FPGAs OnlyXilinx Design Download Cables Probe 3Global Clock Resources Fpga Family Number Destination Pins Fpga Design TipsDesign Size and Performance Global Clock Distribution Data Feedback and Clock Enable 12 Gated Clock 13Synchronous Design Using Data Feedback Counters Q0. . . .Q7 Q8. . . .Q15 Other Synchronous Design ConsiderationsQ0. . . .Q7Q8. . . .Q15 Tcl Tcl Overview Accessing Help Xilinx Tcl Shell Tcl Fundamentals Tcl Fundamentals 1Xilinx Tcl Commands for General Usage Subcommands Xilinx Tcl CommandsXilinx Namespace Project create and manage projects 2Xilinx Tcl Commands for Advanced Scripting Subcommands Tcl Commands for General UsagePartition support design preservation Tcl Commands for General Usage Delete delete a partitionGet get partition properties Partition delete /stopwatch/Instdcm1 Partition get /stopwatch/Instdcm1 preserve New create a new partitionPartition new /stopwatch/Instdcm1 Rerun force partition synthesis and implementation Properties list available partition propertiesPartition properties Set set partition preserve property Run run process task Process run and manage project processes4Process Tasks Project clean Clean remove system-generated project filesProject create and manage projects Close close the ISE project Get get project propertiesGetprocesses get project processes Project close New create a new ISE project Open open an ISE projectProject getprocesses -instance Instdcm1 Project new watchver.ise Set set project properties, values, and options Properties list project propertiesProject properties -process all Set device set device Set family set device familyProject set Map Effort Level high Project set device xc2vp2 Set package set device package Set speed set device speedProject set family Virtex2p Project set package fg256 Timinganalysis generate timing analysis reports Set top set the top-level module/entityDelete delete timing analysis Project set speed Disableconstraints disable timing constraints Disablecpt disable components for path tracing control Enablecpt enable components for path tracing control Timinganalysis enableconstraintsStopwatchtiming TSclk=PERIOD TIMEGROUP\sclk\ Ns High 50.00000% Get get analysis property Timinganalysis enablecpt stopwatchtimingRegsrclk ureg1 ureg2 ureg3 Ascii New new timing analysis Reset reset path filters and constraints Timinganalysis reset stopwatchtimingRun run analysis Saveas save analysis report Set set analysis properties Setconstraint set constraint for custom analysisTiminganalysis set stopwatchtiming Analysisspeed Timinganalysis setconstraint stopwatchtiming Setendpoints set source and destination endpointsPeriod 13 sclk Setquery set up net or timegroup report Setfilter set filter for analysisTiminganalysis setfilter stopwatchtiming nets Exclude uregnet1 uregnet2 uregnet3 Showsettings generate settings report Xfile manage project filesAdd add file to project Example Get get project file properties Remove remove file from projectXfile add *.vhd /mysource/mysubdir timing.ucf Xfile get timestamp stopwatch.vhd Tcl Commands for Advanced Scripting Collection create and manage a collectionAppendto add objects to a collection Xfile remove stopwatch.vhd Tcl Commands for Advanced Scripting Copy copy a collectionSet colVar1 search * -type instance Set colVar2 $colVar1 Equal compare two collections Set colVar2 collection copy $colVar1Set colVar2 search /top/T* -type instance Collection equal $colVar1 $colVar2 Foreach iterate over elements in a collection Get get collection property Index extract a collection object Properties list available collection propertiesSet item collection index $colVar Object name $item Set set the property for all collections Removefrom remove objects from a collectionCollection properties Object get object information Sizeof show the number of objects in a collectionCollection set displaytype true Collection sizeof $colVar Get get object properties Name name of the objectCollection foreach obj $colVar set objProps Object properties $obj foreach prop $objProps Object name collection index $colVar Properties list object propertiesSet colVar search * -type partition Type type of object Search search and return matching objectsObject type collection index $colVar Project Properties and Options Search /stopwatch -type instance6Project Properties Property Name Description Option Name Synthesis Tool Project Properties and Options NGDBuild Options Option Name Implementation Tool Option Name Implementation Tool Tcl 10 PAR Options Sample Tcl Script for General Usage Example Tcl ScriptsExample Tcl Scripts Tcl Sample Tcl Script for Advanced Scripting 100 PARTGen PARTGen OverviewPARTGen Syntax Partgen options PARTGen Input Files PARTGen Output FilesPARTGen Options Arch Print Information for Specified Architecture PARTGen Options Print a List of Devices, Packages, and Speeds PARTGen Options 2s400e Creates Package file and Partlist Files Nopkgfile No Package FilePname Xcv400 Device V400bg432 Part Partlist File Creates Package and Partlist Files Header Device AttributesPartlist File Part architecture family partname diename packagefilename Select RAM PKG File PKG File Done Logical Design Rule Check Logical DRC Overview Logical DRC Checks Block CheckNet Check Pad Check Name Check Clock Buffer CheckLogical DRC Checks 1Checked Primitive Pins NGD Primitive Pins Checked Primitive Pin Check NGDBuild NGDBuild Overview Converting a Netlist to an NGD File 1NGDBuild Design Flow NGDBuild Syntax NGDBuild Input FilesNGDBuild Syntax Ngdbuild options designname ngdfile.ngd 120 Add PADs to Top-Level Port Signals NGDBuild Output FilesNGDBuild Intermediate Files NGDBuild Options Aul Allow Unmatched LOCs Bm Specify BMM FilesDd Destination Directory Ignore UCF File Insertkeephierarchy Libraries to SearchNGDBuild Options Synopsys Modular assemble Module Assembly Modular initial Initial Budgeting of Modular DesignModular assemble -pimpath pimdirectorypath Usepimmodulename1 -usepimmodulename2 Modular module Active Module Implementation Nt Netlist Translation TypeModular module -active modulename Pimcreate pimdirectory -ncd designnamerouted.ncd Sd Search Specified Directory Ignore LOC ConstraintsAllow Unexpanded Blocks Uc User Constraints File Ur Read User Rules FileVerbose Report All Messages Uc ucffile.ucf 128 MAP MAP Overview MAP Syntax Map options infile.ngd pcffile.pcf MAP Output Files MAP Input FilesMAP Input Files MAP Options 1Map Options and Architectures Bp Map Slice Logic Pack CLBsMAP Options 1Map Options and Architectures Cpackfactor Cm Cover Mode Detail Write Out Detailed MAP ReportEquivalentregisterremoval Remove Redundant Registers Cm area speed balanced Gm Guide Mode Gm incremental Guide Mode incrementalGf Guide NCD File Globalopt Global Optimization Ignorekeephierarchy Ignore Keephierarchy Properties Ir Do Not Use RLOCs to Generate RPMsIse ISE Project File Map to Input Functions No logic replication Output File Name Ol Overall Effort Level Olstdmedhigh Pr Pack Registers in I/O No Register OrderingRegisterduplication Duplicate Registers Retiming Register Retiming During Global Optimization Tx Transform Buses Timing Timing-Driven Packing and PlacementTx on off aggressive limit MAP Process Do Not Remove Unused LogicXe Extra Effort Level MAP Process Register Ordering Register Ordering Data01 Addr02 Atod03 Dtoa04 Guided Mapping 3Guided Mapping Simulating Map Results Simulating Map Results 4Logical Circuit Representation MAP Report MRP File MAP Report MRP File 148 Development System Reference Guide 149 Type Block GND Xstgnd IOB 152 Halting MAP Halting MAP 154 Physical Design Rule Check DRC Overview DRC Syntax DRC Input FileDRC Output File DRC Options Report Incomplete Programming DRC ChecksDRC Checks DRC Errors and Warnings PAR Place and Route Overview PAR Flow PAR Process PlacingRouting Timing-driven PAR Par input.ncd output.ncd Command Line ExamplesPar -k previous.ncd reentrant.ncd pref.pcf Guided PAR Guided PAR PCI Cores PAR Syntax PAR Input FilesPAR Output Files PAR Syntax 1Effort Level Options Function Range Default General Options Function Range DefaultPAR Options Ol value for the router Guide Options Function Range Default PAR Options 2General Options Function Range DefaultExistingfile Detailed Listing of Options Execute Commands FileGf Guide NCD File Gm Guide Mode Intstyle Integration StyleRe-Entrant Routing PAR Options Multi-Tasking Mode Number of PAR IterationsNopad No Pad Ol Overall Effort Level No Placement Power Power Aware PARPl Placer Effort Level No Routing Number of Results to Save Starting Placer Cost TableUb Use Bonded I/Os Overwrite Existing Files Performance Evaluation Mode PAR ReportsXe Extra Effort Level PAR Reports Place and Route Report File Development System Reference Guide 175 Ing score in parenthesis Development System Reference Guide 177 Placer effort levelrouter effort levelcost table number Multi Pass Place and Route MpprPar -n 3 -pl high -rl std address.ncd output.dir Select I/O Utilization and Usage Summary Importing the PAD File InformationGuide Reporting Multi Pass Place and Route Mppr Best Performance Mode Xplorer Xplorer Syntax Timing Closure ModeXplorer Xplorer Input Files Xplorer Output FilesXplorer Options 5Xplorer Options Function Xplorer Report Xplorer 5Xplorer Options Function 184 ReportGen ReportGen SyntaxReportGen Input Files ReportGen Output Files ReportGen Options Option Usage FunctionIsexflowsilent Padfmt padcsvtxt Turns Engine PAR Multi-Tasking Option Turns Engine OverviewTurns Engine PAR Multi-Tasking Option Par -m nodefilename -ol high -n 10 mydesign.ncd output.dir Turns Engine Syntax Turns Engine Input Files Limitations Turns Engine Output FilesSystem Requirements Turns Engine Environment Variables Debugging Rsh machinename Screen Output Node Status JOB Time Halting PAR Halting PAR 196 XPower XPower Overview XPower Syntax Files Used by XPowerFpga Designs Cpld Designs Using XPower Using XPowerVCD Data Entry Rename Power Report Other Methods of Data EntryLimit Ls List Supported Devices Specify Settings XML Input File Specify VCD fileTb Turn On Time Based Reporting Wx Write XML File Power Reports Command Line ExamplesStandard Reports Detailed Reports Power ReportsAdvanced Reports 204 PIN2UCF PIN2UCF Overview PIN2UCF Flow PIN2UCF Syntax PIN2UCF Input FilesPIN2UCF Output Files PIN2UCF Syntax PIN2UCF Options PIN2UCF ScenariosWrite to a Report File Outfile.ucf Existing Pinlock section. 210 Trace Trace Overview Trace Syntax Trace Input FilesTrce options design.ncd constraint.pcf Trce -runmacro.xtm design.ncd constraint.pcf Input files to Trace Trace Output FilesTrace Output Files Generate an Error Report Trace OptionsAdvanced Analysis Fastpaths Report Fastest Paths Nodatasheet No Data Sheet Limit Timing ReportOutput Timing Report File Name Trace Options Run Run Timing Analyzer Macro Change SpeedSkew Analyze Clock Skew for All Clocks Skew Stamp Generates Stamp timing model files Report Uncovered PathsStampstampfile design.ncd Ulimit Trace Command Line Examples Generate a Verbose ReportXml XML Output File Name Vlimit Trace Reports Trace Reports Net Delay Constraints Path Delay ConstraintsTiming Verification with Trace Net Skew Constraints Clock Skew and Setup Checking 1Path Delay Constraint Terminology Definition 2Clock Skew and Setup Checking Terminology Terms Definition 2Clock Skew Example 3Clock Passing Through Multiple Buffers Reporting with Trace 5Error reporting for failed timing constraints Data Sheet Report Development System Reference Guide 227 BSLOT0 D0S Guaranteed Setup and Hold Reporting Report Legend Setup Times Hold Times Summary Report Without a Physical Constraints File Specified Trce -o summary.twr ramb16s1.ncd Trce -o summary1.twr ramb16s1.ncd clkperiod.pcf Development System Reference Guide 233 Trce -e 3 ramb16s1.ncd clkperiod.pcf -o errorreport.twr Development System Reference Guide 235 236 Development System Reference Guide 237 BUFGMUX.I0 Offset Constraints Offset Constraints Offset in Header Offset in Constraint ExamplesOffset in Path Details Offset in Detailed Path Data Offset In with Phase Shifted Clock Offset in Detail Path Clock Path Development System Reference Guide 243 Offset OUT Constraint Examples Offset OUT Header Offset OUT Path Details Offset OUT Detail Clock Path Offset OUT Detail Path Data Period Constraints Period Constraints ExamplesPeriod Header Period Constraints Period Path Period Path Details Period Constraint with Phase Period Path with Phase Halting Trace Minimum Period Statistics Speedprint Speedprint Overview Specify Temperature Speedprint SyntaxSpeedprint Options Min Display Minimum Speed Data Speedprint Example Commands Speedprint Example CommandsCommand Description Speedprint Example Reports Lvttl Fast BitGen BitGen Overview Option Output File BitGen SyntaxLoutfilename.ll Moutfilename.msk Boutfilename.rbt BitGen Output Files BitGen Input FilesBitGen Input Files BitGen Options Create Rawbits File Bd Update Block Rams Set ConfigurationBitgen -goptionsetting design.ncd design.bit design.pcf Do Not Run DRC ActiveReconfig ActivateGCLKBinary CclkPin ConfigRate Compress DCMShutdown DCIUpdateModeDebugBitstream DisableBandgap DONEcycleDonePin DonePipe DriveDone EncryptGclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 GSRcycle GWEcycle GTScycleHswapenPin Key0, Key1, Key2, Key3, Key4, Key5 KeyFile Keyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5LCKcycle M0Pin M1Pin M2PinMatchcycle PartialGCLK PartialMask0, PartialMask1, PartialMask2 PartialLeftPartialRight Persist PowerdownPin ProgPinReadBack Security SEURepair StartCBCStartKey StartupClk TckPin TdiPinTdoPin TmsPin UnusedPin No BIT FileUserID Create a Logic Allocation File Generate a Mask FileCreate a Partial Bit File Overwrite Existing Output File 276 BSDLAnno BSDLAnno Overview BSDLAnno Syntax BSDLAnno Input FilesBSDLAnno Output Files BSDLAnno Options BSDLAnno File Composition Entity DeclarationGeneric Parameter BSDLAnno File Composition Logical Port Description Package Pin-Mapping Scan Port Identification USE StatementTAP Description Bsdl File Modifications for Single-Ended Pins Boundary Register Description Explanation Boundary Scan Behavior in Xilinx Devices Modifications to the Designwarning SectionHeader Comments BSDLAnno BSDLAnno version number PROMGen PROMGen Overview PROMGen Syntax PROMGen Input FilesPROMGen Output Files Promgen options PROMGen Options Add BIT FIles Prom FormatLoad Prom File File1.bit file2.bit Prom Size Template FileLoad Upward Ver Version Enable Compression Bit Swapping in Prom Files PROMGen Examples PROMGen Examples 292 IBISWriter IBISWriter Overview IBISWriter Syntax Ibiswriter options infile outfile.ibs IBISWriter Input Files IBISWriter Output FilesIBISWriter Options Set Reference Voltage Ml Multilingual Support Architecture Option Value Description Pin Generate Package Parasitics IBISWriter Options 298 CPLDfit CPLDfit Overview CPLDfit Input Files CPLDfit SyntaxCPLDfit Output Files CPLDfit Options Inputs Number of Inputs to Use During Optimization Iostd Specify I/O StandardKeepio Prevent Optimization of Unused Inputs Loc Keep Specified Location Constraints Nofbnand Disable Use of Foldback Nands Nogclkopt Disable Global Clock OptimizationNogsropt Disable Global Set/Reset Optimization Nogtsopt Disable Global Output-Enable Optimization Power Set Power Mode Optimize Optimize Logic for Density or SpeedSpecify Xilinx Part Pinfbk Use Pin Feedback Terminate Set to Termination Mode Unused Set Termination Mode of Unused I/OsSlew Set Slew Rate Wysiwyg Do Not Perform Optimization 306 Tsim Tsim Syntax Tsim Input Files TAEngine TAEngine Overview TAEngine Syntax 1TAEngine Design Flow TAEngine Options Detail Detail ReportIopath Trace Paths Specify Output Filename 312 Hprep6 1Hprep6 Design Flow Hprep6 Options Hprep6 SyntaxAutosig Automatically Generate Signature Nopullup Disable Pullups Specify Signature Value for ReadbackProduce ISC File Tmv Specify Test Vector File 316 NetGen NetGen Overview NetGen 1NetGen Output File Types Input Design File NetGen Simulation Flow NetGen Functional Simulation FlowNetGen Supported Flows NetGen Simulation Flow NetGen Timing Simulation Flow Syntax for NetGen Functional SimulationOutput files for NetGen Functional Simulation Ngcbuildoptions toplevelnetlistfile outputngcfile Fpga Timing Simulation Syntax for NetGen Timing SimulationNetGen Timing Simulation Flow Output files for Fpga Timing Simulation Cpld Timing SimulationInput files for Cpld Timing Simulation Output files for Cpld Timing Simulation Options for NetGen Simulation Flow Mhf Multiple Hierarchical Files Insertppbuffers Insert Path Pulse BuffersModule Simulation of Active Module Ofmt Output Format Pcf PCF FileChange Speed Sim Generate Simulation Netlist Ti Top Instance Name Tm Top Module NameTp Bring Out Global 3-State Net as Port Insertglbl Insert glbl.v Module Ne No Name Escaping Pf Generate PIN FileSdfanno Include $sdfannotate Sdfpath Full Path to SDF File VHDL-Specific Options for Functional and Timing Simulation NetGen Equivalence Checking Flow Xon Select Output Behavior for Timing ViolationsNetGen Equivalence Checking Flow Xon truefalse Syntax for NetGen Equivalence Checking Input files for NetGen Equivalence Checking Options for NetGen Equivalence Checking Flow Output files for NetGen Equivalence CheckingEcn Equivalence Checking Module Verification of Active Module Ngm Design Correlation File NetGen Static Timing Analysis FlowNetGen Static Timing Analysis Flow Output files for Static Timing Analysis Input files for Static Timing AnalysisSyntax for NetGen Static Timing Analysis Options for NetGen Static Timing Analysis Flow 336 Preserving and Writing Hierarchy Files Sta Generate Static Timing Analysis NetlistPreserving and Writing Hierarchy Files Modulename .sim Modulename .ecn Modulename .sta Testbench File Dedicated Global Signals in Back-Annotation SimulationHierarchy Information File Global Signals in Vhdl Netlist Global Signals in Verilog NetlistDedicated Global Signals in Back-Annotation Simulation 340 Xflow Xflow Overview Xflow Syntax 1XFLOW Design Flow Xflow Input Files Xflow Input Files Xflow Output Files Xflow Output Files 1XFLOW Output Files FPGAs and CPLDs 2XFLOW Output Files FPGAs Assemble Module Assembly Xflow Flow TypesXflow Flow Types 3XFLOW Output Files CPLDs Config Create a BIT File for FPGAs ConfigoptionfileEcn Create a File for Equivalence Checking 4Option Files for -assemble Flow Type Description Fit Fit a Cpld Fsim Create a File for Functional Simulation5Option Files for -ecn Flow Type Description 6Option Files for -fit Flow Type Description Implement Implement an Fpga 7Option Files for -fsim Flow TypeXflow -p xc2v250fg256-5 -fsim genericverilog.opt testclk.v Implement optionfile Initial Initial Budgeting of Modular Design Xflow Flow Types 8Option Files for -implement Flow TypeInitial budget.opt Xflow -p xc2v250fg256-5 -initial budget.opt top.edf Moduleoptionfile -activemodulename Module Active Module Implementation9Option Files for -module Flow Type Mppr Multi-Pass Place and Route for FPGAs Sta Create a File for Static Timing Analysis10Option Files for -mppr Flow Type Description 11Option Files for -sta Flow Type Description Synthesis Types SynthSynthoptionfile Tsim Create a File for Timing Simulation Option Files for -synth Flow Types12Option Files for -synth Flow Type Description Testclk.prj Flow Files 13Option Files for -tsim Flow Type Description Flow File Format Fpga Flag Enabled Disabled TriggersExports Reports User Command Blocks End Program programname Xflow Option Files Option File Format Xflow Options Active Active ModuleEd Copy Files to Export Directory Specify a Global Variable Norun Creates a Script File Only Change Output File NameOoutputfilename Xflow -implement balanced.opt -o newname testclk.edf Pd PIMs Directory Rd Copy Report FilesPdpimdirectory Rdreportdirectory Using Xflow Flow Types in Combination Running XflowWd Specify a Working Directory Running Smart Flow Using the Xilxflowpath Environment Variable Using the SCR, BAT, or TCL FileRunning Xflow 366 Data2MEM Data2MEM Overview Data2MEM Syntax Data2MEM Input and Output FilesBlock RAM Memory Map .bmm files Executable and Linkable Format .elf files Debugging Information Format Dwarf .drf files Memory .mem filesBit .bit files Verilog .v files 1Data2MEM Command Line Options Description Data2MEM OptionsVhdl .vhd files UCF .ucf files Data2MEM Options 1Data2MEM Command Line Options Pp filename Xilinx Development System Files Name Type Produced By Description Appendix MOD Ascii Trace NKY TCL Ascii 378 EDIF2NGD, and NGDBuild EDIF2NGD EDIF2NGD Design Flow EDIF2NGD Syntax EDIF2NGD Input FilesEDIF2NGD Output Files Edif2ngd options ediffile ngofile EDIF2NGD Options Add PADs to Top-Level Port SignalsAul Allow Unmatched LOCs Libraries to Search Part NumberIgnore LOC Constraints Llibname NGDBuild NGDBuild and the Netlist Readers NGDBuild Netlist Launcher Netlister Bus MatchingBus Naming Conventions Busnameindex DI3 Netlist Launcher Netlister Netlist Launcher Rules Files User Rules FileUser Rules and System Rules User Rules Format Development System Reference Guide 389 System Rules File Value Types in Key Statements Rules File Examples Example 1 Edfrule System Rule Example 2 User Rule Example 3 User Rule Example 4 User Rule NGDBuild File Names and LocationsNGDBuild File Names and Locations 394 Glossary Abel Asic Bitstream BlockBonded Boundary scan Buft CAE CLB Cmos Configuration ContentionCombinatorial logic Compiler Cpld Daisy chainDangling bus Dangling net DRC DSP EDA Edif Fdsd EpromFifo Fmap Fpga Global Set/Reset net Gate arrayGlobal buffers Global 3-state net HDL Ibuf Ieee IFD Jedec LSB MSB NCD NGM PAL PIM PLD Prom RAM RPM ROMRTL SDF standard delay format Set/resetSignal Startup symbol TCL Trace Tsim TTL Wire VhdlVital Xtclsh 422